中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

34 records (took 0.028 seconds)

    Digital generator producing clock signal of period proportional to binary number received by digital oscillator, comprising components connected in series
    12.
    发明专利
    Digital generator producing clock signal of period proportional to binary number received by digital oscillator, comprising components connected in series 未知

    公开(公告)号：FR2816136A1

    公开(公告)日：2002-05-03

    申请号：FR0013897

    申请日：2000-10-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAILHARD BRUNO ,  FERRAND OLIVIER

    IPC: H03K3/03 ,  H03L7/099

    Abstract: The generator comprises an oscillator producing a clock signal (CKHF) on the basis of N decoded control signals SD(1), SD(2), ..., SD(N) received from a comparator and obtained by comparing the period of the clock signal to a desired period which is e.g. a multiple of a reference signal period. The oscillator (40) comprises N=2n components C(0), C(1), ..., C(N-1) connected in series, where the low-weight component C(0) delivers the clock signal. At least one component (C(i) of weight i comprises two inputs (a,b), two outputs (c,d), and three branches: the first branch (a-d) contains an interrupter INT(i+1) which is closed when the control signal SD(i+1) is active; the second branch (a-c) contains an interrupter INTA(i) and at least one, in particular two inverters connected in series; the third branch (b-d) contains an interrupter INTB(i); the interrupters INTA(i) and INTB(i) are open when the control signal SD(i) is active. The low-weight component C(0) comprises an odd number (NB) of inverters, where the number is greater than or equal to 1. The component C(i) of weight i greater than 1 comprises an even number (NC) of inverters connected in series in branch (a-c) and/or in branch (b-d); or odd numbers of inverters in branches (a-c) and (b-d). The branches (a-d) are identical and contain the same number of inverters. The components C(i) of weight i in the range from 1 to N-1 are identical. The generator comprises a comparator which receives the clock signal (CKIHF) and delivers the control number with n bits in the form N=2n of binary signals which are decoded; the control number is increased/decreased if the period of the clock signal is below/above the desired period, and remains constant otherwise.

    14.
    发明专利
    未知

    公开(公告)号：FR2797070A1

    公开(公告)日：2001-02-02

    申请号：FR9910150

    申请日：1999-07-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  FERRAND OLIVIER ,  GAILHARD BRUNO

    IPC: G06K17/00 ,  G06K7/00 ,  G06K7/01 ,  G06K19/07 ,  H01H3/16

    Abstract: The invention concerns a smart card reader (20) comprising a housing for receiving the card, a microprocessor (30), means for connecting the microprocessor to the smart card inserted in the housing and a voltage source (21). The invention is characterised in that the microprocessor (30) is electrically powered by the voltage source (21) via a switch (24) which is normally open, and is arranged to be closed when the card is completely inserted in the housing. The invention is particularly applicable to viewer card readers powered by an electric battery.

    Analogue generator producing controlled high-frequency clock signal on basis of low-frequency clock signal, comprising electronic devices including sampler connected in phase-locked loop
    15.
    发明专利
    Analogue generator producing controlled high-frequency clock signal on basis of low-frequency clock signal, comprising electronic devices including sampler connected in phase-locked loop 未知

    公开(公告)号：FR2816134A1

    公开(公告)日：2002-05-03

    申请号：FR0013901

    申请日：2000-10-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAILHARD BRUNO ,  FERRAND OLIVIER

    IPC: H03L7/089 ,  H03L7/18 ,  H03L7/091 ,  H03K19/00

    Abstract: The generator (30) comprises a frequency divider (32), a phase comparator (34) delivering the control signals (UP, DOWN), a sampler (35), a voltage generator (36) delivering the control voltage (VCK), and an oscillator (30) delivering the high-frequency clock signal (CKHF) whose frequency depends on the control voltage; the devices are connected in series, and the output of the oscillator is connected to the input of the frequency divider forming the phase-locked loop, and also to the clock input of sampler. The precision of generator can be substantially increased by connecting a separate oscillator (40) to the clock input of sampler. The sampler (35) delivers the sampled control signals (UPech, DOWNech) to the voltage generator (36), which delivers the control voltage (VCK) as a function of the sampled control signals. The sampler (35) contains a counter receiving a validation signal and delivering a sampling signal when the number of counted pulses reaches a set number, and the counter is reset when it reaches another set number; two logic gates receiving the sampling signal on one input and each one of the control signals on the other input, and delivering the samples control signals; and a third logic gate receiving the two control signals and delivering the validation signal. The period of sampling signal is less than or equal to the desired period.

    17.
    发明专利
    未知

    公开(公告)号：FR2797070B1

    公开(公告)日：2001-09-28

    申请号：FR9910150

    申请日：1999-07-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  FERRAND OLIVIER ,  GAILHARD BRUNO

    IPC: G06K17/00 ,  G06K7/00 ,  G06K7/01 ,  G06K19/07 ,  H01H3/16

    Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

    18.
    发明专利
    未知

    公开(公告)号：FR2797120B1

    公开(公告)日：2001-09-14

    申请号：FR9910149

    申请日：1999-07-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： RUAT LUDOVIC ,  FERRAND OLIVIER

    IPC: G04F1/00 ,  H03K21/08 ,  G06G1/04

    Abstract: The invention relates to a digital timer (20) comprising a binary counter (21) driven by a counting clock signal (Hc), the counter (21) presenting a stabilization time after each counting pulse, and means for delivering a detection signal (DS2) with a predetermined value when a counting order (N) is reached by the counter. According to the invention, the timer comprises wired logic means (22) arranged for detecting, at the output of the counter, a counting value (N-1) which is immediately before the counting order (N) in relation to the counting direction, and delivering an intermediate signal (DS1) with a predetermined value, as well means (24) for sampling the intermediate signal (DS1) at a moment when the counter receives the next counting pulse.

    20.
    发明专利
    未知

    公开(公告)号：FR2832819B1

    公开(公告)日：2004-01-02

    申请号：FR0115259

    申请日：2001-11-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： FERRAND OLIVIER ,  GAILHARD BRUNO

    IPC: G05F3/26 ,  G05F3/30

    Abstract: The current source has a circuit with a branch (b1) fixing a reference voltage (V1), a branch (b2) fixing a reference current and a branch (b3) supplying a current obtained from current mirror (M2,M3), with a second current mirror (M1,M2) that is connected to ground through resistances (R1,R2) in series with transistors (Q) to compensate current variations by selecting resistance values.

Patent Agency Ranking