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公开(公告)号：DE602004007835T2
公开(公告)日：2008-04-10
申请号：DE602004007835
申请日：2004-01-14
Applicant: ST MICROELECTRONICS SA
Inventor： PADMANABHA GOSAGAN , DAVIDESCU DRAGOS , ROCHE FRANCK
Abstract: The microprocessor has a CPU with registers containing a contextual data and a pointer of stack (SP, SPH, SPL). A memory (MEM2) has a stack (STK) for backup of the contextual data. The CPU is arranged to backup the contextual data contained in a variable number of registers according to a flag value stored in a register (CCR, CR) to backup, at a time of shifting from one program to another. An independent claim is also included for a process of management of stack of microprocessor.
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公开(公告)号：FR2857111A1
公开(公告)日：2005-01-07
申请号：FR0308053
申请日：2003-07-02
Applicant: ST MICROELECTRONICS SA
Inventor： FERRAND OLIVIER , DAVIDESCU DRAGOS
Abstract: The microcontroller has a reset circuit (3) that selectively generates a reset signal for resetting a microprocessor (2). A detection device (4) has an input (5) for receiving a critical logic signal from the microprocessor. The detection device has an output that applies a reset command on the reset circuit, upon detecting a change in the logic state of the logic signal.
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公开(公告)号：FR2793087A1
公开(公告)日：2000-11-03
申请号：FR9905396
申请日：1999-04-28
Applicant: ST MICROELECTRONICS SA
Inventor： DAVIDESCU DRAGOS
Abstract: The operational amplifier comprises an inverting input (EI) and a non-inverting input (ENI), each controlling respective transistors (Q1,Q2) of differential pair. The output source voltages (Vos1,Vos2) are directed to complementary inputs of an output or an intermediary circuit. There are six transistors (Q1-1, Q1-2, Q1-3, Q2-1, Q2-2, Q2-3) which can be selectively connected in circuit for the correction of output offset voltages, by adjustment of correction signals. Each correction element is constituted by a correction transistor or trimmer (Q1-1, Q1-2, Q1-3, Q2-1, Q2-2, Q2-3) with the provision of a selective connection in parallel to the respective input transistor (Q1,Q2). The response characteristic of a correction transistor is weak in comparison to that of the corresponding input transistor (Q1,Q2), so that the output signal of the correction transistor is about 0.5-10% of that of the input transistor for the same input signal. Each input route (EI,ENI) comprises a set of n correction transistors, where n is greater than one, e.g. n = 3, where each correction transistor can independently be connected in parallel to the corresponding input transistor. The n correction transistors are associated in a geometric progression, and the response value corresponds to a binary sequence. The correction transistors are connected by switching elements (S1,S2,S3,S4) having control inputs for binary signals (B1,B2,B3,Sel). The operational amplifier is implemented by CMOS (Complementary Metal Oxide Semiconductor) technology allowing an amplitude of input signal in the range from low (Vss) to high (Vdd) values of the supply voltage. A circuit for the correction of offset voltage comprises the proposed operational amplifier, and the means for determination of output voltage, for an application of reference voltage to one input (ENI), for a selective connection of two inputs (EI,ENI) and for programming the connection of correction elements including a data register. The correction to offset voltage is determined by an iteration in cycles comprising the offset voltage measuring step followed by the correction element selection step. The offset voltage is measured at two instants, firstly in a voltage repeater configuration with a resistive loop connected to the inverted input and a reference voltage applied to the non inverted input, and secondly with inputs (EI,ENI) mutually connected via a resistor. Independent claims are included for a method of correction of the offset voltage.
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公开(公告)号：FR2895101A1
公开(公告)日：2007-06-22
申请号：FR0512818
申请日：2005-12-16
Applicant: ST MICROELECTRONICS SA
Inventor： LINK JEAN FRANCOIS , DAVIDESCU DRAGOS , LENDRE SANDRINE
IPC: G06F1/04
Abstract: Dispositif multifonctionnel temporisateur/compteur d'évènements (TIMER) comprenant au moins un compteur (CNT) piloté par un signal d'horloge (CLK), et un registre de contrôle (REG_CTRL) comprenant au moins un nombre binaire destiné à au moins définir un comportement dudit compteur (CNT).Le dispositif comprend également un module de fonction (MF) comprenant au moins une entrée (TRG) de réception d'un signal de synchronisation et une entrée de réception d'au moins un signal de commande de fonction (TMS), ledit module de fonction (MF) étant apte à modifier ledit nombre binaire en fonction au moins dudit signal de synchronisation et dudit signal de commande de fonction (TMS).
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公开(公告)号：FR2809884A1
公开(公告)日：2001-12-07
申请号：FR0007016
申请日：2000-05-31
Applicant: ST MICROELECTRONICS SA
Inventor： DAVIDESCU DRAGOS
Abstract: The device comprises a clock circuit (10) delivering the synchronization pulses (CK), a delay circuit (12), a counter (18), and a voltage generator (14) controlled by the counter so to produce a sawtooth waveform (24) which is applied to the delay circuit for modifying the phase of synchronization pulses. The original synchronization pulses from the clock circuit (10) are applied to the delay circuit (12) which outputs the modified clock signal (CK'), and to the counter (18) which is a divider producing a signal each time when N pulses are counted. In the second embodiment, the voltage generator is a digital-analogue converter, and the counter (18) provides the state signals of different stages. The delay circuit (12) contains a set of N stages in cascade, where each stage comprises an inverter circuit followed by a capacitor, and the output of the set of stages is connected to a re-leveling circuit. The inverter circuit comprises a pair of transistors, p-MOS and n-MOS, with the gates connected together to the clock signal input, the drains to the capacitor pole which is the stage output, and the source of the first transistor to the sawtooth voltage input.
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Patent Agency Ranking
公开(公告)号：DE602004007835D1
公开(公告)日：2007-09-13
申请号：DE602004007835
申请日：2004-01-14
Applicant: ST MICROELECTRONICS SA
Inventor： PADMANABHA GOSAGAN , DAVIDESCU DRAGOS , ROCHE FRANCK
Abstract: The microprocessor has a CPU with registers containing a contextual data and a pointer of stack (SP, SPH, SPL). A memory (MEM2) has a stack (STK) for backup of the contextual data. The CPU is arranged to backup the contextual data contained in a variable number of registers according to a flag value stored in a register (CCR, CR) to backup, at a time of shifting from one program to another. An independent claim is also included for a process of management of stack of microprocessor.
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公开(公告)号：FR2877515A1
公开(公告)日：2006-05-05
申请号：FR0411486
申请日：2004-10-28
Applicant: ST MICROELECTRONICS SA
Inventor： GAILLARD PATRICE , DAVIDESCU DRAGOS
IPC: H03M1/44
Abstract: L'invention concerne un convertisseur analogique / numérique de a bits, pour convertir un courant analogique initial (IN) en une donnée associée (DATA). Selon l'invention, le convertisseur comprend a cellules associées en série et, pour n compris entre a-1 et 0, une cellule de rang n :• compare un courant (I1(n+1)) reçu d'une cellule de rang n+1 avec un courant de référence (IMAX/2a-n) de valeur décroissante avec le rang n de la cellule,• produit le résultat de la comparaison sous la forme d'un bit de donnée (OUT(n), OUTC(n)), et• fournit à la cellule (ET(n-1)) de rang immédiatement inférieur n-1 un courant qui, en fonction du résultat de la comparaison, est égal soit au courant reçu (I1(n)) soit à un courant complémentaire (2*IMAX/2a-n - I1(n) du courant reçu par rapport à deux fois le courant de référence.
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公开(公告)号：DE60203271D1
公开(公告)日：2005-04-21
申请号：DE60203271
申请日：2002-04-02
Applicant: ST MICROELECTRONICS SA
Inventor： LINK JEAN-FRANCOIS , DAVIDESCU DRAGOS
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公开(公告)号：FR2851349A1
公开(公告)日：2004-08-20
申请号：FR0301879
申请日：2003-02-17
Applicant: ST MICROELECTRONICS SA
Inventor： PADMANABHAN GOSAGAN , DAVIDESCU DRAGOS , ROCHE FRANCK
Abstract: The microprocessor has a CPU with registers containing a contextual data and a pointer of stack (SP, SPH, SPL). A memory (MEM2) has a stack (STK) for backup of the contextual data. The CPU is arranged to backup the contextual data contained in a variable number of registers according to a flag value stored in a register (CCR, CR) to backup, at a time of shifting from one program to another. An independent claim is also included for a process of management of stack of microprocessor.
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公开(公告)号：FR2845783A1
公开(公告)日：2004-04-16
申请号：FR0212794
申请日：2002-10-15
Applicant: ST MICROELECTRONICS SA
Inventor： RUAT LUDOVIC , DAVIDESCU DRAGOS
Abstract: The programmable clock generator (CKGEN2) is able to deliver a frequency (Fs) equal to a primary frequency (Fo) divided by a nominated decimal number (M,M1,M3) and also provide that the duration of (Ni) impulses is MasteriskNi times the primary period (To). The clock uses a modulation circuit (MODCT), a modulation distribution circuit (DISCT) and two divisors (DIV1,DIV2) Independent claims are also included for the following (1) A circuit for asynchronous transmission/reception of data (UART) which is driven by an over sampled clock signal provided by the programmable clock generator (2) A method for producing a clock signal whose frequency is equal to a primary frequency divided by a decimal number and also for modulating the produced impulses such that the duration of a number of successive impulses is equal to a multiple of the primary period
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