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    11.
    发明专利
    未知

    公开(公告)号：DE69930365D1

    公开(公告)日：2006-05-11

    申请号：DE69930365

    申请日：1999-12-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： BELOT DIDIER

    IPC: H01L21/76 ,  H01L27/06 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/12 ,  H04B1/28

    Abstract: A built-in circuit includes a semiconductor substrate (SB) with a bottom part (PSB) and upper layer (CSB) strongly doped that the bottom part. A first block (BC3) and a second block (BC1) are formed in the upper part of the substrate. An isolating device is arranged closed to the second block (BC1) and includes an isolating circuit (CRS) linked to the bottom part of the substrate (PSB). A mass connection (PTMD1) provide a minimal impedance at a given frequency.

    12.
    发明专利
    未知

    公开(公告)号：FR2864729B1

    公开(公告)日：2006-05-05

    申请号：FR0315480

    申请日：2003-12-29

    Applicant: ST MICROELECTRONICS SA

    Inventor： CARPENTIER JEAN FRANCOIS ,  TILHAC CYRILLE ,  BELOT DIDIER

    IPC: H03H9/17 ,  H03H3/04 ,  H03J3/18 ,  H03J3/20 ,  H03J3/24 ,  H03L5/00 ,  H03L7/00

    Abstract: The circuit has a bulk acoustic resonator (212) with two resonance frequencies. An inductor (213) cancels the one of the resonance frequencies. A capacitance adjusting unit (211), e.g. a varactor, allows the tuning of the resonator to be adjusted at the other resonant frequency. The inductor is placed in series with the resonator and adjusted at a series resonance frequency of the resonator to reinforce adjustment at the parallel-resonant frequency. An independent claim is also included for a method of fabricating an integrated circuit including an acoustic resonator component.

    13.
    发明专利
    未知

    公开(公告)号：DE69825527T2

    公开(公告)日：2005-09-01

    申请号：DE69825527

    申请日：1998-05-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： BELOT DIDIER

    IPC: H04L7/033

    Abstract: The receiving circuit for bits transmitted on an asynchronous signal (Din) consists of a circuit which provides a reconstructed clock from an asynchronous signal. The clock is designed to sample the asynchronous signal to form a synchronised output signal (Ds). The receiver also has a reception error detection circuit. The error detection circuit consists of a front detector (21, 22, 24, 25), which provides a detection pulse (UP, DN) for each leading edge in a predetermined direction for the asynchronous signal. An alarm circuit (27, 28) generates an warning signal when a leading edge of a synchronous signal (Ds) survives outside a detection pulse (UP, DP).

    15.
    发明专利
    未知

    公开(公告)号：FR2847726B1

    公开(公告)日：2005-03-04

    申请号：FR0214905

    申请日：2002-11-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： KNOPIK VINCENT ,  BELOT DIDIER

    IPC: H01Q9/04 ,  H01Q23/00

    Abstract: The module has a dielectric substrates (6) bearing conducting aerial layer and a substrate (8) bearing circuit units (30) e.g. inductance, capacitor, and a conductive shield layer (10). Thickness and nature of the substrate are selected by holding account of surface of a conductive layer and stock points, so that the layer (10) is coupled to the earth by a capacitor constituting a short-circuit for the radio frequencies. The conductive shield layer (10) being floating is laid out between the dielectric substrates.

    16.
    发明专利
    未知

    公开(公告)号：FR2820546B1

    公开(公告)日：2003-07-11

    申请号：FR0101524

    申请日：2001-02-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： BELOT DIDIER

    IPC: H01L27/02 ,  H01L29/06 ,  H01L23/66

    Abstract: A structure of protection of a first area of a semiconductor wafer including a substrate of a first conductivity type against high-frequency noise likely to be injected from components formed in the upper portion of a second area of the wafer, includes a very heavily-doped wall of the first conductivity type having substantially the depth of the upper portion. The wall is divided into three heavily-doped strips of the first conductivity type separated and surrounded by medium-doped intermediary strips of the first conductivity type. The distance between the heavily-doped strips being of the order of magnitude of the substrate thickness.

    17.
    发明专利
    未知

    公开(公告)号：FR2820546A1

    公开(公告)日：2002-08-09

    申请号：FR0101524

    申请日：2001-02-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： BELOT DIDIER

    IPC: H01L27/02 ,  H01L29/06 ,  H01L23/66

    Abstract: The invention concerns a structure for protecting a first zone of a semiconductor wafer comprising a substrate (11) having a first type of conductivity against high frequency disturbances liable to be injected from components formed in the upper part of a second zone of the wafer, comprising a highly-doped wall of the first type of conductivity having substantially the depth of said upper part. The invention is characterised in that said wall is divided into three highly-doped strips (21) of the first type of conductivity separated and enclosed by moderately-doped intermediate strips (23) of the first type of conductivity, the distance between the highly-doped end strips being of the order of magnitude of the substrate thickness.

    18.
    发明专利
    未知

    公开(公告)号：DE69523120D1

    公开(公告)日：2001-11-15

    申请号：DE69523120

    申请日：1995-11-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： BELOT DIDIER

    IPC: H03M9/00 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H04Q3/00

    Abstract: The device receives incoming digital words (DATAP) which arrive in parallel and performs multiplexing to produce serialised output words (DATAS) for transmission. Multiplexing is performed using a chain of five differential registers (12-15,4) which route the digital signals and three multiplexers (MUX1,MUX2,MUX3). The multiplexers are synchronised by synchronising signals (CLK1, CLK2,CLK3) which are sampling signals derived from the synchronous divider of a PLL (2). The input register is synchronised from a clock signal (CLK0) which is derived from the incoming digital stream. The output register is synchronised by a synchronous signal (CLK4) from the PLL.

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