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公开(公告)号：FR2799044A1
公开(公告)日：2001-03-30
申请号：FR9912148
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The method for selecting an access line of a memory of EEPROM type with serial access, implemented in the form of an integrated circuit, includes a selection from the group of access lines (AL0-AL7) of the same nature, e.g. the bit lines or the word lines, by a line code for p (=3) bits associated with each access line of the group, and comprises the following steps: (a) the activation of all access lines of the group; (b) the reception, by the intermediary of an input of serial data (D1), of a bit (Ai) of determined rank of code of access line to select; and (c) the de-activation of a part of other access lines as a function of bit (Ai). The latter two steps, (b) and (c), are repeated successively p times for each bit of line code, so that at the end of p iterations only the selected access line remains activated. The access lines which are de-activated at step (c) are the access lines which line code presents a bit rank i of value different from that of the received bit at step (b). The group of access lines comprises 2p lines, and half of lines still activated is de-activated at each iteration. All access lines are simultaneously activated, at step (1). The bits of line code received at step (b) are included in the address bits of memory word on which an operation defined by an instruction received according to a serial protocol is carried out. The set of access lines is an ordered set, according to increasing or decreasing binary values of associated line codes. A decoder of access lines implementing the method comprises latches (10-107), each coupled to an access line (AL0-AL7), each latch comprising switching, activation and de-activation means operated as a function of selection signals (Bit0,Bit1,Bit2,Bit0 bar, Bit1 bar, Bit2 bar), the means for putting all latches into active state, and the means for the generation of selection signals as a function of bits of line code. The switching means of a latch comprise an inverter connected between input and output, thee activation means comprise a controlled interrupter, and the de-activation means comprise the decoding means including p MOS transistors with the gates connected to the selection inputs, and one with the gate connected to the output of latch. The means for the generation of selection signals comprise 2p logic gates of NAND type (NE1-NE6), the first p gates receiving p bits of the line code, and the second p gates receiving the logic inverses of p bits of the line code. A memory in the form of an integrated circuit comprises a planar memory array with memory cells accessible by a group of bit lines and a group of word lines, a decoder of bit lines (COLDEC) and a decoder of word lines (ROWDEC).
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公开(公告)号：DE60041317D1
公开(公告)日：2009-02-26
申请号：DE60041317
申请日：2000-11-22
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , DEVIN JEAN
IPC: H03K17/16
Abstract: The integrated circuit (20) comprises an output MOS transistor (Tout) connected to a data transmission line (31) presenting a determined capacitance (Cbus), where the gate of transistor is driven by a logic circuit (11) present in the integrated circuit which receives a determined supply voltage (Vccd), and a gate-biasing circuit (41) for lowering the gate-source voltage (Vgs) in the on-state of transistor with respect to the supply voltage, which would be set by the output of logic circuit in the absence of gate-biasing circuit. The lengthening of fall time while retaining the operating point (Vol, Iol) also includes an increase in the width/length ratio (W/L) of transistor gate in an implementation stage. The gate-biasing circuit (41) comprises two transistors connected in series, each connected as a diode. The first transistor of MOS type is substantially identical to the output transistor. The gate-source voltage (Vgs) is less than 2 V to set the transistor in the on-state. The output transistor (Tout) has the ratio W/L corresponding to the operating point in low state in conformity with the specifications of 12C bus and the fall time (Tfall) of output signal equal at least to 20 nanoseconds. The method for lengthening the fall time includes the lowering of gate-source voltage (Vgs), and the increased ratio W/L of transistor gate. The integrated circuit is in the form of an EEPROM, and the output stage (40) is laid out to deliver the data read in the memory.
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公开(公告)号：FR2821974A1
公开(公告)日：2002-09-13
申请号：FR0103284
申请日：2001-03-12
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.
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公开(公告)号：FR2803142B1
公开(公告)日：2002-02-01
申请号：FR9916563
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , DEVIN JEAN
Abstract: The integrated circuit (20) comprises an output MOS transistor (Tout) connected to a data transmission line (31) presenting a determined capacitance (Cbus), where the gate of transistor is driven by a logic circuit (11) present in the integrated circuit which receives a determined supply voltage (Vccd), and a gate-biasing circuit (41) for lowering the gate-source voltage (Vgs) in the on-state of transistor with respect to the supply voltage, which would be set by the output of logic circuit in the absence of gate-biasing circuit. The lengthening of fall time while retaining the operating point (Vol, Iol) also includes an increase in the width/length ratio (W/L) of transistor gate in an implementation stage. The gate-biasing circuit (41) comprises two transistors connected in series, each connected as a diode. The first transistor of MOS type is substantially identical to the output transistor. The gate-source voltage (Vgs) is less than 2 V to set the transistor in the on-state. The output transistor (Tout) has the ratio W/L corresponding to the operating point in low state in conformity with the specifications of 12C bus and the fall time (Tfall) of output signal equal at least to 20 nanoseconds. The method for lengthening the fall time includes the lowering of gate-source voltage (Vgs), and the increased ratio W/L of transistor gate. The integrated circuit is in the form of an EEPROM, and the output stage (40) is laid out to deliver the data read in the memory.
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公开(公告)号：FR2799044B1
公开(公告)日：2001-12-14
申请号：FR9912148
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The method for selecting an access line of a memory of EEPROM type with serial access, implemented in the form of an integrated circuit, includes a selection from the group of access lines (AL0-AL7) of the same nature, e.g. the bit lines or the word lines, by a line code for p (=3) bits associated with each access line of the group, and comprises the following steps: (a) the activation of all access lines of the group; (b) the reception, by the intermediary of an input of serial data (D1), of a bit (Ai) of determined rank of code of access line to select; and (c) the de-activation of a part of other access lines as a function of bit (Ai). The latter two steps, (b) and (c), are repeated successively p times for each bit of line code, so that at the end of p iterations only the selected access line remains activated. The access lines which are de-activated at step (c) are the access lines which line code presents a bit rank i of value different from that of the received bit at step (b). The group of access lines comprises 2p lines, and half of lines still activated is de-activated at each iteration. All access lines are simultaneously activated, at step (1). The bits of line code received at step (b) are included in the address bits of memory word on which an operation defined by an instruction received according to a serial protocol is carried out. The set of access lines is an ordered set, according to increasing or decreasing binary values of associated line codes. A decoder of access lines implementing the method comprises latches (10-107), each coupled to an access line (AL0-AL7), each latch comprising switching, activation and de-activation means operated as a function of selection signals (Bit0,Bit1,Bit2,Bit0 bar, Bit1 bar, Bit2 bar), the means for putting all latches into active state, and the means for the generation of selection signals as a function of bits of line code. The switching means of a latch comprise an inverter connected between input and output, thee activation means comprise a controlled interrupter, and the de-activation means comprise the decoding means including p MOS transistors with the gates connected to the selection inputs, and one with the gate connected to the output of latch. The means for the generation of selection signals comprise 2p logic gates of NAND type (NE1-NE6), the first p gates receiving p bits of the line code, and the second p gates receiving the logic inverses of p bits of the line code. A memory in the form of an integrated circuit comprises a planar memory array with memory cells accessible by a group of bit lines and a group of word lines, a decoder of bit lines (COLDEC) and a decoder of word lines (ROWDEC).
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Patent Agency Ranking
公开(公告)号：FR2799043B1
公开(公告)日：2001-12-14
申请号：FR9912149
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The columns register of a memory in the form of integrated circuit is of EEPROM technology type, and the method for writing a data word with 2p bits, where p is an integer, comprises the following steps: (i) erasing all cells of the word; (ii) loading 2q data to the same number of high-voltage latches (HV1,HV3,HV5,HV7), and loading 2p-2q other data to that number of low-voltage latches (LV0,LV2,LV4,LV6); (iii) programming 2q cells of the words memory (M0,M2,M4,M6) as a function of stored data in the high-voltage latches; and the following steps repeated 2p-q-1 times: (iv) loading 2q other data in the high-voltage latches, which were loaded to the low-voltage latches in step (ii); and (v) programming 2q other cells of the words memory (M1,M3,M5,M7) as a function of data stored in the high-voltage latches. The columns register comprises 2q high-voltage latches, where q is an integer strictly less than p, where each high-voltage latch comprises the means for high voltage storage for the storage of a binary datum, as high programming voltage, e.g. 18 V, or zero voltage, coupled to the mean for conditional and selective switching for carrying the high programming voltage to the determined bit line; and 2p-q low-voltage latches, where each low-voltage latch comprises the means for low voltage storage for the storage of a binary datum as low supply voltage, e.g. 5 V, or zero voltage, and thee means for coupling to the input of one of the high-voltage latches, which is activated for loading the binary datum stored in the low-voltage latch. In particular, the integer p = 3, and q = 2. The means for conditional and selective switching comprise a MOS transistor with n-type conductivity channel, connected by the gate to the output of high-voltage storage means, by the drain to high programming voltage, and to the bit lines (BL0,BL1) by the intermediary of MOS transistors for the purpose of insulation of the bit lines in the read mode and the selection of particular bit line in the write mode. The first and second loading means share at least one loading transistor (TC1,TC2), which are activated simultaneously by at least first loading signal (LOAD1,LOAD2) applied to the gate of loading transistor, connected to a transistor for word selection (TS1) with the gate receiving the word selection signal (COL). The means for high voltage storage in the high-voltage latches comprise two inverters in CMOS technology in antiparallel connection between the high programming voltage and the ground, and the means for low voltage storage comprise analogous components connected between the low supply voltage and the ground. An integrated circuit memory comprises a planar memory with at least 2p cells connected to the respective bit lines, and proposed columns register. A memory comprises several words memory on the same line, and the means for writing to certain or all of words memory simultaneously. The programming step (v) is followed by a step (vi) for bringing to zero the means for storage of low-voltage and high-voltage latches. The steps (i) and/or (iii) to (v) are operated simultaneously for several or all of words memory of the same line of memory cells.
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公开(公告)号：FR2799043A1
公开(公告)日：2001-03-30
申请号：FR9912149
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The columns register of a memory in the form of integrated circuit is of EEPROM technology type, and the method for writing a data word with 2p bits, where p is an integer, comprises the following steps: (i) erasing all cells of the word; (ii) loading 2q data to the same number of high-voltage latches (HV1,HV3,HV5,HV7), and loading 2p-2q other data to that number of low-voltage latches (LV0,LV2,LV4,LV6); (iii) programming 2q cells of the words memory (M0,M2,M4,M6) as a function of stored data in the high-voltage latches; and the following steps repeated 2p-q-1 times: (iv) loading 2q other data in the high-voltage latches, which were loaded to the low-voltage latches in step (ii); and (v) programming 2q other cells of the words memory (M1,M3,M5,M7) as a function of data stored in the high-voltage latches. The columns register comprises 2q high-voltage latches, where q is an integer strictly less than p, where each high-voltage latch comprises the means for high voltage storage for the storage of a binary datum, as high programming voltage, e.g. 18 V, or zero voltage, coupled to the mean for conditional and selective switching for carrying the high programming voltage to the determined bit line; and 2p-q low-voltage latches, where each low-voltage latch comprises the means for low voltage storage for the storage of a binary datum as low supply voltage, e.g. 5 V, or zero voltage, and thee means for coupling to the input of one of the high-voltage latches, which is activated for loading the binary datum stored in the low-voltage latch. In particular, the integer p = 3, and q = 2. The means for conditional and selective switching comprise a MOS transistor with n-type conductivity channel, connected by the gate to the output of high-voltage storage means, by the drain to high programming voltage, and to the bit lines (BL0,BL1) by the intermediary of MOS transistors for the purpose of insulation of the bit lines in the read mode and the selection of particular bit line in the write mode. The first and second loading means share at least one loading transistor (TC1,TC2), which are activated simultaneously by at least first loading signal (LOAD1,LOAD2) applied to the gate of loading transistor, connected to a transistor for word selection (TS1) with the gate receiving the word selection signal (COL). The means for high voltage storage in the high-voltage latches comprise two inverters in CMOS technology in antiparallel connection between the high programming voltage and the ground, and the means for low voltage storage comprise analogous components connected between the low supply voltage and the ground. An integrated circuit memory comprises a planar memory with at least 2p cells connected to the respective bit lines, and proposed columns register. A memory comprises several words memory on the same line, and the means for writing to certain or all of words memory simultaneously. The programming step (v) is followed by a step (vi) for bringing to zero the means for storage of low-voltage and high-voltage latches. The steps (i) and/or (iii) to (v) are operated simultaneously for several or all of words memory of the same line of memory cells.
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公开(公告)号：FR2858457A1
公开(公告)日：2005-02-04
申请号：FR0309456
申请日：2003-07-31
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: The method involves applying a memory cell state fixation pulse on a floating gate of a transistor of the cell of a non-volatile memory. A high voltage signal for adjusting the cell state fixing portion is applied on a ramp voltage generation circuit (301) of the memory from outside the memory at a preset duration. The cell state fixing portion is adjusted at the preset duration. An independent claim is also included for a non volatile memory.
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公开(公告)号：FR2854967A1
公开(公告)日：2004-11-19
申请号：FR0305742
申请日：2003-05-13
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: Device, such as semiconductor memory or EEPROM, communicates following a communication protocol that forecasts transmission of acknowledgement signals (ACK) at predefined instants. The operating mode is identified by a shift in time of the moment of transmission of the ACK signal relative to the forecast moment. An independent claim is also included for a device for identifying the mode of operation of a device.
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公开(公告)号：FR2853781A1
公开(公告)日：2004-10-15
申请号：FR0304365
申请日：2003-04-09
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , CHEHADI MOHAMAD , NAURA DAVID
IPC: H03K3/011 , H03K3/012 , H03K3/3565
Abstract: The trigger has a latch with four transistors, where latch has two thresholds, and an input (IN) and an output (OUT) for forming an input and an output of the trigger. The latch also has a middle point between a supply terminal and an output of the latch. A negative feedback acts on the middle point to fix one of the thresholds according to supply potential. One threshold is a function of a stable reference potential.
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