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公开(公告)号：JP2001155492A
公开(公告)日：2001-06-08
申请号：JP2000299140
申请日：2000-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: PROBLEM TO BE SOLVED: To reduce occupied area of a shift register of an EEPROM integrated circuit serial access type memory. SOLUTION: This memory is provided with a data input DI, a data output D0, a memory plane MM constituted of memory words, a set LAT of a column register in which one register is combined with at least one memory word, a first means operated for loading directly binary data of a binary word received at a data input Di to each storage/switching latches HV0-HV7 of a column register R1 combined with memory words M0-M7 during writein operation of a binary word for the prescribed memory words M0-M7, and/or a second means operated for reading out continuously binary data stored in a memory cell of a memory word transmitting each read-out binary data to the data output D0 of a memory with a direct serial form during read-out operation of binary words in memory words.
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公开(公告)号：JP2001118394A
公开(公告)日：2001-04-27
申请号：JP2000281033
申请日：2000-09-14
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , ZINK SEBASTIEN , BERTRAND BERTRAND
Abstract: PROBLEM TO BE SOLVED: To decrease the number of required high voltage latch without lengthening excessively a page mode access time. SOLUTION: In a page mode write-in method of a non-volatile memory being electrically erasable and programmable in an integrated circuit, a written page corresponds to a column of a memory array. This method comprises write-in of information elements for selecting a page written in a storage latch combined with columns of a non-volatile memory array, an initial stage including writing each data written in a page in a temporary storage device, and a write-in stage selecting a row of a non-volatile memory array conforming to contents of the temporary storage device. The page mode write-in means is provided with one latch per one column of a non-volatile memory array, and a control logic circuit outputting a row selecting signal in accordance with contents of the temporary storage device at a stage at which a column of the non-volatile memory array is written, in order to storing page selection information elements.
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公开(公告)号：DE60043565D1
公开(公告)日：2010-02-04
申请号：DE60043565
申请日：2000-09-05
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The columns register of a memory in the form of integrated circuit is of EEPROM technology type, and the method for writing a data word with 2p bits, where p is an integer, comprises the following steps: (i) erasing all cells of the word; (ii) loading 2q data to the same number of high-voltage latches (HV1,HV3,HV5,HV7), and loading 2p-2q other data to that number of low-voltage latches (LV0,LV2,LV4,LV6); (iii) programming 2q cells of the words memory (M0,M2,M4,M6) as a function of stored data in the high-voltage latches; and the following steps repeated 2p-q-1 times: (iv) loading 2q other data in the high-voltage latches, which were loaded to the low-voltage latches in step (ii); and (v) programming 2q other cells of the words memory (M1,M3,M5,M7) as a function of data stored in the high-voltage latches. The columns register comprises 2q high-voltage latches, where q is an integer strictly less than p, where each high-voltage latch comprises the means for high voltage storage for the storage of a binary datum, as high programming voltage, e.g. 18 V, or zero voltage, coupled to the mean for conditional and selective switching for carrying the high programming voltage to the determined bit line; and 2p-q low-voltage latches, where each low-voltage latch comprises the means for low voltage storage for the storage of a binary datum as low supply voltage, e.g. 5 V, or zero voltage, and thee means for coupling to the input of one of the high-voltage latches, which is activated for loading the binary datum stored in the low-voltage latch. In particular, the integer p = 3, and q = 2. The means for conditional and selective switching comprise a MOS transistor with n-type conductivity channel, connected by the gate to the output of high-voltage storage means, by the drain to high programming voltage, and to the bit lines (BL0,BL1) by the intermediary of MOS transistors for the purpose of insulation of the bit lines in the read mode and the selection of particular bit line in the write mode. The first and second loading means share at least one loading transistor (TC1,TC2), which are activated simultaneously by at least first loading signal (LOAD1,LOAD2) applied to the gate of loading transistor, connected to a transistor for word selection (TS1) with the gate receiving the word selection signal (COL). The means for high voltage storage in the high-voltage latches comprise two inverters in CMOS technology in antiparallel connection between the high programming voltage and the ground, and the means for low voltage storage comprise analogous components connected between the low supply voltage and the ground. An integrated circuit memory comprises a planar memory with at least 2p cells connected to the respective bit lines, and proposed columns register. A memory comprises several words memory on the same line, and the means for writing to certain or all of words memory simultaneously. The programming step (v) is followed by a step (vi) for bringing to zero the means for storage of low-voltage and high-voltage latches. The steps (i) and/or (iii) to (v) are operated simultaneously for several or all of words memory of the same line of memory cells.
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公开(公告)号：FR2822286A1
公开(公告)日：2002-09-20
申请号：FR0103659
申请日：2001-03-19
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , CHEHADI MOHAMAD , NAURA DAVID
Abstract: The electrically programmable erasable memory has cells (CEij) connected to word lines (WLi) and bit lines (BLj) arranged in columns (COLk). There is a selection column lock (LSCIk). Each lock column selected has a unit delivering a detection of a grid control signal, a signal selecting bit lines, as a function of the output locking element during the phases of programming and read oF the memory cells.
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公开(公告)号：FR2798767B1
公开(公告)日：2001-12-14
申请号：FR9911601
申请日：1999-09-16
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
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Patent Agency Ranking
公开(公告)号：FR2799045A1
公开(公告)日：2001-03-30
申请号：FR9912150
申请日：1999-09-29
Applicant: ST MICROELECTRONICS SA
Inventor： ZINK SEBASTIEN , BERTRAND BERTRAND , NAURA DAVID
Abstract: The integrated circuit memory is of EEPROM type, comprising the data input (D1) and the data output (DO), a planar memory (MM) organized inn words memory (M0-M7), a set of columns registers (LAT) associated with words memory, the first means regarding the write operation for loading the binary data of binary word received at the data input directly to latches (HV0-HV7) of columns register associated with the words memory, and the second means regarding the read operation for a successive reading of binary data stored in the memory cells of words memory and a direct delivery of each binary data in serial form to the data output. The latches for storage and switching (HV0-HV7) comprise each two inverters in antiparallel connection for the storage of binary datum in the form of higher programming voltage or the zero voltage, coupled to the means for conditional switching in the form of two transistors connected in series for carrying the higher programming voltage to the determined bit line, and the loading means in the form of two transistors with the common source connection. The first and second means also comprise the means for an application of selection signals (Bit0-Bit7) to the loading means of latches of each columns register, and the means for loading the data into latches which act via the register selection means in the form of a transistor common to all the latches of the determined columns register. The means for the loading data into latches are common to all columns registers of the memory. The second means comprise a single read line, READLINE, connecting the set of columns registers (LAT) to a read circuit, SENSEAMP. The read circuit comprises only one read amplifier to detect a current flowing in the read line. The memory comprises only one output data line, OUTPUTDATALINE, connecting the output of read circuit to the data output (DO) via a buffer circuit, OUTBUF. The first means comprise only one input data line, INPUTDATALINE, connecting the data input (DI) to the set of columns registers (LAT) via a buffer circuit, INBUF.
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公开(公告)号：DE60226800D1
公开(公告)日：2008-07-10
申请号：DE60226800
申请日：2002-03-05
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
IPC: G11C16/12
Abstract: A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.
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公开(公告)号：FR2854967B1
公开(公告)日：2005-08-05
申请号：FR0305742
申请日：2003-05-13
Applicant: ST MICROELECTRONICS SA
Inventor： NAURA DAVID , BERTRAND BERTRAND , CHEHADI MOHAMAD
Abstract: Device, such as semiconductor memory or EEPROM, communicates following a communication protocol that forecasts transmission of acknowledgement signals (ACK) at predefined instants. The operating mode is identified by a shift in time of the moment of transmission of the ACK signal relative to the forecast moment. An independent claim is also included for a device for identifying the mode of operation of a device.
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公开(公告)号：FR2853781B1
公开(公告)日：2005-06-10
申请号：FR0304365
申请日：2003-04-09
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , CHEHADI MOHAMAD , NAURA DAVID
IPC: H03K3/011 , H03K3/012 , H03K3/3565
Abstract: The trigger has a latch with four transistors, where latch has two thresholds, and an input (IN) and an output (OUT) for forming an input and an output of the trigger. The latch also has a middle point between a supply terminal and an output of the latch. A negative feedback acts on the middle point to fix one of the thresholds according to supply potential. One threshold is a function of a stable reference potential.
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公开(公告)号：FR2803142A1
公开(公告)日：2001-06-29
申请号：FR9916563
申请日：1999-12-23
Applicant: ST MICROELECTRONICS SA
Inventor： BERTRAND BERTRAND , DEVIN JEAN
Abstract: The integrated circuit (20) comprises an output MOS transistor (Tout) connected to a data transmission line (31) presenting a determined capacitance (Cbus), where the gate of transistor is driven by a logic circuit (11) present in the integrated circuit which receives a determined supply voltage (Vccd), and a gate-biasing circuit (41) for lowering the gate-source voltage (Vgs) in the on-state of transistor with respect to the supply voltage, which would be set by the output of logic circuit in the absence of gate-biasing circuit. The lengthening of fall time while retaining the operating point (Vol, Iol) also includes an increase in the width/length ratio (W/L) of transistor gate in an implementation stage. The gate-biasing circuit (41) comprises two transistors connected in series, each connected as a diode. The first transistor of MOS type is substantially identical to the output transistor. The gate-source voltage (Vgs) is less than 2 V to set the transistor in the on-state. The output transistor (Tout) has the ratio W/L corresponding to the operating point in low state in conformity with the specifications of 12C bus and the fall time (Tfall) of output signal equal at least to 20 nanoseconds. The method for lengthening the fall time includes the lowering of gate-source voltage (Vgs), and the increased ratio W/L of transistor gate. The integrated circuit is in the form of an EEPROM, and the output stage (40) is laid out to deliver the data read in the memory.
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