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    1.
    发明专利
    未知

    公开(公告)号：DE60041317D1

    公开(公告)日：2009-02-26

    申请号：DE60041317

    申请日：2000-11-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： BERTRAND BERTRAND ,  DEVIN JEAN

    IPC: H03K17/16

    Abstract: The integrated circuit (20) comprises an output MOS transistor (Tout) connected to a data transmission line (31) presenting a determined capacitance (Cbus), where the gate of transistor is driven by a logic circuit (11) present in the integrated circuit which receives a determined supply voltage (Vccd), and a gate-biasing circuit (41) for lowering the gate-source voltage (Vgs) in the on-state of transistor with respect to the supply voltage, which would be set by the output of logic circuit in the absence of gate-biasing circuit. The lengthening of fall time while retaining the operating point (Vol, Iol) also includes an increase in the width/length ratio (W/L) of transistor gate in an implementation stage. The gate-biasing circuit (41) comprises two transistors connected in series, each connected as a diode. The first transistor of MOS type is substantially identical to the output transistor. The gate-source voltage (Vgs) is less than 2 V to set the transistor in the on-state. The output transistor (Tout) has the ratio W/L corresponding to the operating point in low state in conformity with the specifications of 12C bus and the fall time (Tfall) of output signal equal at least to 20 nanoseconds. The method for lengthening the fall time includes the lowering of gate-source voltage (Vgs), and the increased ratio W/L of transistor gate. The integrated circuit is in the form of an EEPROM, and the output stage (40) is laid out to deliver the data read in the memory.

    2.
    发明专利
    未知

    公开(公告)号：FR2859041A1

    公开(公告)日：2005-02-25

    申请号：FR0309987

    申请日：2003-08-18

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN

    IPC: G11C8/20 ,  G11C11/22 ,  G11C16/22

    Abstract: The circuit has a non-volatile memory zone (3) for storing identification codes, and a programming pin (4) for programming the memory zone. A register (5) that can be programmed only once, stores a state indicating whether the memory zone has been programmed. A module (6) blocks the programming of the memory zone when the register indicates that the memory zone has been programmed. An independent claim is also included for a method of using a memory circuit.

    Flash memory erasable by page and method for data storaage, comprising array with counter and sectors, and circuits for reading page address and incrementing counter
    4.
    发明专利
    Flash memory erasable by page and method for data storaage, comprising array with counter and sectors, and circuits for reading page address and incrementing counter 未知

    公开(公告)号：FR2816751A1

    公开(公告)日：2002-05-17

    申请号：FR0014743

    申请日：2000-11-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN ,  DEVIN JEAN

    IPC: G11C16/06 ,  G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

    Abstract: The page-erasable flash memory (MEM1) comprises a flash memory array (FMA) containing floating-gate transistors whose gates are connected to the word lines, where the transistors connected to the same word line form a page, a row decoder (XDEC1) connected to the word lines, and control circuits which apply a positive erase voltage (Ver+) for a page erasing to the source of the drainn electrodes of all transistors of one of the sectors (S1,S2,...S8) comprisingn the page. The row deecodere contains voltage adapters for applying, during the page erassing, a negative erase voltage (Ver-) to the gates of transistors of the page to be erased, and a positive inhibition voltage (Vinhib) to the gates of transistors of at least one of the other pages. The inhibition voltage is below the positive erase voltage. In the process of the page erasing, a polarization voltage (Vpol) is equal to the negative erase voltage (Ver-) and a row polarization voltage (Vpex) is equa to the inhibition voltage (Vinhib); in the process of word reaading the polarization voltage is equal to the ground potential and the row polarization voltage is equal to a read voltage (Vread). The polarization voltages are delivered by a polarization module (PMP) by the intermediary of a switching element to the voltage adapters receiving the page selection signals and contained in the row deecoder (XDEC1). Each voltage adapter contains an output inverter staage and a control stage with an exclusive-OR gate receiving the selection signal and the erase signal. The circuits for the control of the voltage threshold of transistors and for reprogramming when the voltage threshold is below a set value include a counter (CMPT) formed by at least one row of transistors, the address counter read circuits including a shift register (SREG), a conversion circuit (CONVC) and a zero-detector (DETZ), and the counter increment circuits including the shift register and a register with latches (LT). The page addrses read circuits comprise the counter word-to-word read circuits including a counter decoder (CDEC), a sense amplifier (SA), the zero-detector and a column address counter (CAC), the page address high-value bit circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit circuits including the column address counter and a multiplexer (MUX2). The page control includes the reading of a word of the page by applying the first read voltage (Vread), the reading of the same word of the page by applying the second read, that is verify, voltage (Vvrfy), the comparison of the two readings, and the reprogramming if the two readings are different. The positive erase voltage (Ver+) is applied to the source or the drain electrodes of transistors by the intermediary of a material forming the channel of transistors.

    Flash memory and method for data storage, comprising circuits for control of threshold voltage of memory cells and reprogramming when below set verification value
    5.
    发明专利
    Flash memory and method for data storage, comprising circuits for control of threshold voltage of memory cells and reprogramming when below set verification value 未知

    公开(公告)号：FR2816750A1

    公开(公告)日：2002-05-17

    申请号：FR0014742

    申请日：2000-11-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN ,  DEVIN JEAN

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

    Abstract: The page-erasable flash memory (MEM1) comprises a flash memory array (FMA), which contains transistors with floating gates connected to the word lines forming pages belonging to sectors (S1,S2...S8), and the control circuits comprising a counter (CMPT) formed by at least one row of transistors, the page address reading circuits including a shift register (SREG), a conversion circuit (CONVC), and a zero-detector (DETZ), and the counter increment circuits including the shift register and a programming register containing latches (LT). The circuits are connected so that the reprogramming of programmed transistors is carried out when the threshold voltage of transistors is below a set verification voltage. The page address reading circuits also comprise the counter word reading circuits including a counter decoder (CDEC), a sense amplifier (SA), the zero-detector, and a column address counter (CAC), the page address high-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the conversion circuit and a multiplexer (MUX1), and the page address low-value bit delivery circuits including the column address counter and a multiplexer (MUX2). The circuits for the counter increment are connected for the programming of at least one counter transistor without erasing other transistors, and the transistor programmed at each increment is the next according to the direction of reading the counter. The page control circuits also comprise a row decoder (XDEC1) and the sense amplifier for reading a word of page by applying the first read voltage (Vread), for reading the same word of page by applying the second read, that is verify, voltage (Vvrfy), for comparing the two readings by a comparator (COMP), and for the reprogramming of transistors if the two readings (W1,W2) are different. The page erasing is by applying a positive erase voltage (Ver+) to the source or the drain electrodes of all transistors of the sector comprising the page. The row decoder (XDEC1) contains adapters for applying a polarization or a negative erase voltage (Vpol,Ver-) to the gates of transistors of the page to be erased, and for applying a positive inhibition or row decoder voltage (Vinhib,Vpcx) to the gates of transistors of one or more pages not to be erased. The adapter circuits receive a page selection signal and deliver the positive voltage (Vpcx) when teh page is not selected and the memory is in the erase mode, or when the page is selected and the memory is not in the erase mode, and the polarization voltage (Vpol), which is below the positive voltage (Vpcx), when the page is selected and the memory is in the erase mode, or when the page is not selected and the memory is not in the erase mode. During the page erasing the polarization voltage (Vpol) is equal to the erase voltage (Ver-) and the positive voltaage (Vpcx) is equal to the inhibition voltage (Vinhib); during the word reading the polarization voltage is equal to the ground potential and the positive voltage is equal to the read voltage. Each adapter circuit contains an output inverter stage and a control stage with an exclusive-OR gate. The positive erase voltage (Ver+) is applied to the source or the drain electrodes of transistors by the intermediary of a material forming the channel of transistors.

    7.
    发明专利
    未知

    公开(公告)号：FR2803142B1

    公开(公告)日：2002-02-01

    申请号：FR9916563

    申请日：1999-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： BERTRAND BERTRAND ,  DEVIN JEAN

    IPC: H03K17/16 ,  H03K17/08 ,  G11C7/12 ,  G11C16/02 ,  H03K17/14

    Abstract: The integrated circuit (20) comprises an output MOS transistor (Tout) connected to a data transmission line (31) presenting a determined capacitance (Cbus), where the gate of transistor is driven by a logic circuit (11) present in the integrated circuit which receives a determined supply voltage (Vccd), and a gate-biasing circuit (41) for lowering the gate-source voltage (Vgs) in the on-state of transistor with respect to the supply voltage, which would be set by the output of logic circuit in the absence of gate-biasing circuit. The lengthening of fall time while retaining the operating point (Vol, Iol) also includes an increase in the width/length ratio (W/L) of transistor gate in an implementation stage. The gate-biasing circuit (41) comprises two transistors connected in series, each connected as a diode. The first transistor of MOS type is substantially identical to the output transistor. The gate-source voltage (Vgs) is less than 2 V to set the transistor in the on-state. The output transistor (Tout) has the ratio W/L corresponding to the operating point in low state in conformity with the specifications of 12C bus and the fall time (Tfall) of output signal equal at least to 20 nanoseconds. The method for lengthening the fall time includes the lowering of gate-source voltage (Vgs), and the increased ratio W/L of transistor gate. The integrated circuit is in the form of an EEPROM, and the output stage (40) is laid out to deliver the data read in the memory.

    10.
    发明专利
    未知

    公开(公告)号：DE69700258D1

    公开(公告)日：1999-07-15

    申请号：DE69700258

    申请日：1997-02-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： DEVIN JEAN

    IPC: G11C11/56

    Abstract: The Multi-Level Memory has a matrix (1) of non volatile memory cells (1) memorising two bits of information. The matrix is divided into sectors which are addressable (3,4) and programmable (6,7,8). Read and Write circuits (5) are associated with the matrix. A real time clock (14) updates a command circuit (2) which periodically refreshes (2A) the memory cells.

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