公开(公告)号：DE60128646D1

公开(公告)日：2007-07-12

申请号：DE60128646

申请日：2001-11-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE ,  WUIDART SYLVIE

IPC: G06F12/14 ,  G06F21/55

Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.

公开(公告)号：FR2879296A1

公开(公告)日：2006-06-16

申请号：FR0452964

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE

IPC: G01R31/26 ,  H01L21/66

Abstract: L'invention concerne un procédé et un circuit de protection d'au moins un élément (41) d'un circuit intégré (20), conditionnant le fonctionnement de l'élément à protéger, à l'état d'un signal (VAL) conditionné par un élément à programmation irréversible dont l'état est fixé lors d'un test sous pointes du circuit intégré.

公开(公告)号：FR2819070B1

公开(公告)日：2003-03-21

申请号：FR0017261

申请日：2000-12-28

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE ,  WUIDART SYLVIE

IPC: G06F21/55 ,  G06F12/14 ,  G06K19/073

Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.

公开(公告)号：FR2804521A1

公开(公告)日：2001-08-03

申请号：FR0001061

申请日：2000-01-27

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  MALHERBE ALEXANDRE ,  MARINET FABRICE

IPC: G06F13/42 ,  G06K19/07 ,  G06F1/04 ,  H04L7/00 ,  H03L7/00

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

公开(公告)号：DE60128646T2

公开(公告)日：2008-01-31

申请号：DE60128646

申请日：2001-11-03

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE ,  WUIDART SYLVIE

IPC: G06F12/14 ,  G06F21/55

Abstract: The protection process include detection of the status of a timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The timer is de-activated if a predetermined sequence of processes has been executed normally. If this is not the case, a counter is incremented and when this reaches a threshold the data may be protected or erased. The process for protection of an integrated circuit against pirate copying comprises a series of stages executed by the circuit, before a predetermined sequence of processes. The stages include detection of the status of at least one timer (5); controlling the triggering of the timer if the timer is not active; and blocking the device if the timer is active. The integrated circuit executes the process of de-activating the timer, if a predetermined sequence of processes has been executed normally. A further process is activated by the integrated circuit, if the timer is detected to be active; this consists of modifying the value of a counter in a protected non-volatile region of the memory (EEPROM), comparing the value of this counter with a predetermined threshold, and effecting a process of protection of stored confidential data if the counter has attained the threshold value. The protection may be achieved by erasing the confidential data.

公开(公告)号：FR2875949A1

公开(公告)日：2006-03-31

申请号：FR0452183

申请日：2004-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： WUIDART LUC ,  MARINET FABRICE

IPC: H01L23/58 ,  G11C7/24 ,  H01L27/02

Abstract: L'invention concerne la protection d'un circuit intégré en conditionnant le démarrage de tout ou partie du circuit à la présence d'une clé (KEY), enregistrée de façon non volatile dans le circuit postérieurement à sa fabrication et dépendant d'au moins un premier paramètre (A, ID) présent de façon non volatile dans le circuit à l'issue de sa fabrication.

公开(公告)号：FR2875623A1

公开(公告)日：2006-03-24

申请号：FR0452140

申请日：2004-09-23

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE

IPC: G06K19/073 ,  H01L21/28

Abstract: L'invention concerne la génération d'un identifiant d'une puce (2) portant au moins un circuit intégré, consistant à provoquer une découpe d'au moins un trajet conducteur (4) par découpe de la puce, la position du trait de coupe (3) par rapport au bord de la puce conditionnant l'identifiant.

公开(公告)号：FR2868577A1

公开(公告)日：2005-10-07

申请号：FR0450630

申请日：2004-03-31

Applicant: ST MICROELECTRONICS SA

Inventor： MARINET FABRICE ,  BOTELLA CAMILLE

IPC: G06F21/75 ,  G06F21/77 ,  G06K19/073 ,  G07F7/10 ,  G08B13/14 ,  H01L23/00 ,  H01L23/58 ,  H01L27/00

Abstract: L'invention concerne un circuit de détection d'attaque par contact d'une puce de circuit intégré comprenant un moyen (1) d'application d'un signal aléatoire à une première borne (V) d'au moins un premier chemin conducteur (2) formé dans au moins un premier niveau de métallisation de la puce, un moyen (4) de comparaison du signal appliqué avec un signal présent sur une deuxième borne (W) du chemin, et un moyen (3) pour retarder l'instant de comparaison par rapport à l'instant d'application, d'une durée (T) supérieure ou égale au retard de propagation (τ) apporté par le premier chemin.

公开(公告)号：FR2838233A1

公开(公告)日：2003-10-10

申请号：FR0204184

申请日：2002-04-04

Applicant: ST MICROELECTRONICS SA

Inventor： DUVAL BENJAMIN ,  MARINET FABRICE

IPC: G11C17/18 ,  G11C17/16 ,  G11C11/34

Abstract: The method for programming a row of antifuse memory cells (SEL1-SELN) connected in parallel comprises a step of breakdown of at least N antifuse elements (AF1-AFN) contained in the memory cells, which becomes conducting by breakdown. The breakdown of an antifuse element is carried out by applying a breakdown voltage (Vhv) onto the anode of the antifuse element. The antifuse elements are broken down sequentially in groups of P elements, where P is less than N and at least equal to 1. The antifuse elements of the same group receives the breakdown voltage simultaneously, and the breakdown of the next group of the antifuse elements follows the breakdown of the preceding group of the antifuse elements. The antifuse elements are broken down individually one after another when P = 1. The value of P is chosen so that the total time (TP) of the breakdown of N antifuse elements is optimal. The number P is not constant during the programming of the row of memory cells. The method comprises a step of detecting the breakdown of the antifuse elements manifested in a voltage on the cathode of the antifuse elements higher than a determined threshold (Vref). The cathode voltage and the reference voltage are input to a comparator (CMP), which delivers a signal (SHIFT) to the control input of a shift register (SREG) comprising N cells in cascade (C1 - CN) for controlling switches in pairs: SWA1 and SWB1, ..., SWAN and SWBN. The antifuse memory in the form of an integrated circuit implements the method as claimed, and comprises means for sequentially applying the breakdown voltage to the groups of antifuse elements.

公开(公告)号：FR2817361B1

公开(公告)日：2003-01-24

申请号：FR0015309

申请日：2000-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： MALHERBE ALEXANDRE ,  MARINET FABRICE

IPC: G06F7/58 ,  G06K19/073 ,  H03K3/84 ,  G06K19/07

Abstract: Random signal generator comprises an MOS transistor as an electronic noise source. The MOS transistor is operated with a drain source current having a random component and has means for producing a binary random signal from the random drain source current. The current channel is arranged to be curved or S shaped by suitable doping. The invention also relates to an integrated circuit with a binary signal generator based on an MOS transistor. The circuit has suitable connections for connecting to other circuits. An Independent claim is made for a method for generating a random signal from an electronic noise source, in which an MOS transistor with an S or screw shaped channel is used.