中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.023 seconds)

    11.
    发明专利
    未知

    公开(公告)号：DE69834315D1

    公开(公告)日：2006-06-01

    申请号：DE69834315

    申请日：1998-02-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CHIOZZI GIORGIO ,  ANDREINI ANTONIO

    IPC: H01L27/07 ,  H01L29/06 ,  H01L21/76 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78

    Abstract: The n-channel VDMOS transistor described is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region (13) and has its gate electrode connected to the gate electrode (17) of the VDMOS transistor, its source region in common with the source region (9) of the VDMOS transistor, and its drain region (30, 31) connected to the p-type junction-isolation region (14). The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

    13.
    发明专利
    未知

    公开(公告)号：DE69410436D1

    公开(公告)日：1998-06-25

    申请号：DE69410436

    申请日：1994-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  CHIOZZI GIORGIO

    IPC: H01L27/06 ,  H01L21/8222 ,  H03H11/40 ,  H03K4/06 ,  H03K4/50

    Abstract: A circuit for dividing a reference current (Ir) is composed by an n number of transistors (Q1,Q2,Q3) connected in cascade, in a Darlington configuration, between current generator and a fractionary current output node (V2) and by N+k, where k is an integer different from zero, directly biased diodes (D1-D4) in series, connected between the generator and said fractionary current output node. The circuit does not employ current mirrors and conveniently all transistors may have the minimum size of the process, which also minimizes the effects of leakage currents. Additionally, means may be used for compensating the leakage currents from the tubs of the transistors. The circuit is useful as a capacitance multiplier, or as a slow ramp generator in a large number of design situations. Independency from intrinsic parameters of the transistors used and/or from temperature of operation may be provided by employing a specifically designed reference current generating means. Several embodiments are described.

    14.
    发明专利
    未知

    公开(公告)号：DE69406108D1

    公开(公告)日：1997-11-13

    申请号：DE69406108

    申请日：1994-04-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  CHIOZZI GIORGIO

    IPC: H03F1/30 ,  H03F3/181 ,  H03F3/72 ,  H03G3/34

    Abstract: A low frequency amplifier (30) comprising, in series, a first input stage (2), an intermediate amplifying stage (3) and a final stage (4). The intermediate amplifying stage comprises a capacitor (18) which is discharged when the amplifier is disabled, and is charged to a predetermined bias value when the amplifier is operative. To prevent voltage peaks at the output of the amplifier (30) during the transient interval between the disabled and operating condition of the amplifier, a second input stage (31) is provided which is only turned on during the transient interval, and is connected to the capacitor (18) to detect its voltage and charge it. During the transient interval, the final stage (4) is disabled. Upon the capacitor (18) reaching the predetermined charge value, the second input stage practically turns itself off, and is then disabled; and, at the same time, the first input stage (2) and the final stage (4) are enabled to turn on the amplifier (30).

    16.
    发明专利
    未知

    公开(公告)号：DE69834315T2

    公开(公告)日：2007-01-18

    申请号：DE69834315

    申请日：1998-02-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CHIOZZI GIORGIO ,  ANDREINI ANTONIO

    IPC: H01L27/07 ,  H01L29/06 ,  H01L21/76 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78

    Abstract: The n-channel VDMOS transistor described is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region (13) and has its gate electrode connected to the gate electrode (17) of the VDMOS transistor, its source region in common with the source region (9) of the VDMOS transistor, and its drain region (30, 31) connected to the p-type junction-isolation region (14). The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

    19.
    发明专利
    未知

    公开(公告)号：DE69406108T2

    公开(公告)日：1998-02-12

    申请号：DE69406108

    申请日：1994-04-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BOTTI EDOARDO ,  CHIOZZI GIORGIO

    IPC: H03F1/30 ,  H03F3/181 ,  H03F3/72 ,  H03G3/34

    Abstract: A low frequency amplifier (30) comprising, in series, a first input stage (2), an intermediate amplifying stage (3) and a final stage (4). The intermediate amplifying stage comprises a capacitor (18) which is discharged when the amplifier is disabled, and is charged to a predetermined bias value when the amplifier is operative. To prevent voltage peaks at the output of the amplifier (30) during the transient interval between the disabled and operating condition of the amplifier, a second input stage (31) is provided which is only turned on during the transient interval, and is connected to the capacitor (18) to detect its voltage and charge it. During the transient interval, the final stage (4) is disabled. Upon the capacitor (18) reaching the predetermined charge value, the second input stage practically turns itself off, and is then disabled; and, at the same time, the first input stage (2) and the final stage (4) are enabled to turn on the amplifier (30).

    20.
    发明专利
    未知

    公开(公告)号：DE69727934D1

    公开(公告)日：2004-04-08

    申请号：DE69727934

    申请日：1997-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CHIOZZI GIORGIO ,  TAVAZZANI CLAUDIO

    IPC: H03F3/72 ,  H03F1/00

    Abstract: An integrated power operational amplifier can alternatively be operated in a master or a slave mode, such that a master amplifier can be connected in parallel with one or more slave amplifiers. This arrangement allows very low impedance loads to be driven, as well the heat dissipation to be distributed over a number of devices, thereby raising the maximum dissipation limits of integrated power systems. In addition, by eliminating the ballast resistors, more power can be delivered by the system, for the same supply voltage, and less power dissipated.

Patent Agency Ranking