中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.041 seconds)

    Vdmos transistor
    2.
    发明专利
    Vdmos transistor 有权
    VDMOS晶体管

    公开(公告)号：JPH11274495A

    公开(公告)日：1999-10-08

    申请号：JP1337099

    申请日：1999-01-21

    Applicant: St Microelectronics Srl ,  エスティーマイクロエレクトロニクスエス.アール.エル.

    Inventor： CHIOZZI GIORGIO ,  ANDREINI ANTONIO

    IPC: H01L29/06 ,  H01L21/76 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78 ,  H02M1/00

    CPC classification number: H01L27/0251 ,  H01L29/0619 ,  H01L29/7809 ,  H01L29/7811

    Abstract: PROBLEM TO BE SOLVED: To avoide an overvoltage between a source and a gate in which a gate dielectric of VDMOS(vertical double diffusion MOS) transistors formed in an active region of an integrated circuit which is junctioned and isolated may be damaged or broken.
    SOLUTION: MOS transistors are formed in an active region 13, and the gate electrode is connected to a gate electrode 17 of VDMOS transistors and a source region of the MOS transistors is made common to a source region 9 of the VDMOS trasistors, and drain regions 30, 31 of the MOS transistors are coupled to a junction and isolation region 14. A threshold voltage of the MOS transistors is lower than a breakdown voltage of a gate dielectric of the VDMOS transistors, and the MOS transistors act as a voltage limitter.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：为了避免源极和栅极之间的过电压，其中形成在结合和隔离的集成电路的有源区中的VDMOS（垂直双重扩散MOS）晶体管的栅极电介质可能被损坏或破坏。 解决方案：MOS晶体管形成在有源区13中，栅电极连接到VDMOS晶体管的栅电极17，并且MOS晶体管的源极区域与VDMOS晶体管的源极区9相同，漏区 30,31的MOS晶体管耦合到结和隔离区14.MOS晶体管的阈值电压低于VDMOS晶体管的栅极电介质的击穿电压，并且MOS晶体管用作电压限制器。

    7.
    发明专利
    未知

    公开(公告)号：DE69834315T2

    公开(公告)日：2007-01-18

    申请号：DE69834315

    申请日：1998-02-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CHIOZZI GIORGIO ,  ANDREINI ANTONIO

    IPC: H01L27/07 ,  H01L29/06 ,  H01L21/76 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78

    Abstract: The n-channel VDMOS transistor described is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region (13) and has its gate electrode connected to the gate electrode (17) of the VDMOS transistor, its source region in common with the source region (9) of the VDMOS transistor, and its drain region (30, 31) connected to the p-type junction-isolation region (14). The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

    8.
    发明专利
    未知

    公开(公告)号：DE69834315D1

    公开(公告)日：2006-06-01

    申请号：DE69834315

    申请日：1998-02-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CHIOZZI GIORGIO ,  ANDREINI ANTONIO

    IPC: H01L27/07 ,  H01L29/06 ,  H01L21/76 ,  H01L27/02 ,  H01L29/739 ,  H01L29/78

    Abstract: The n-channel VDMOS transistor described is formed in an n-type active region of an integrated circuit with junction isolation. To prevent over-voltages between source and gate which could damage or destroy the gate dielectric, a p-channel MOS transistor is formed in the same active region (13) and has its gate electrode connected to the gate electrode (17) of the VDMOS transistor, its source region in common with the source region (9) of the VDMOS transistor, and its drain region (30, 31) connected to the p-type junction-isolation region (14). The p-channel MOS transistor has a threshold voltage below the breakdown voltage of the gate dielectric of the VDMOS transistor so that it acts as a voltage limiter.

Patent Agency Ranking