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    18.
    发明专利
    未知

    公开(公告)号：ITUB20153367A1

    公开(公告)日：2017-03-03

    申请号：ITUB20153367

    申请日：2015-09-03

    Applicant: ST MICROELECTRONICS SRL ,  ST MICROELECTRONICS DES & APPL

    Inventor： MANGANO DANIELE ,  CARRANO MICHELE ALESSANDRO ,  DISTEFANO GAETANO ,  FRIED ANTONIN

    IPC: G06F11/10

    Abstract: In an embodiment, a method of managing memories (10) includes: - providing a first (11) memory module and a second memory module (12) each including a first (R1, R2) and a second (R4, R3) partition, - writing first data (DATA1) in the first partition (R1) of the first memory module (11) and second data (DATA2) in the first partition (R2) of the second memory module (12), and - selectively operating the first (11) and second (12) memory modules in a first operating mode or a second operating mode, where: - in the first operating mode, parity bits (PAR1) for the first data (DATA1) are written in the second partition (R3) of the second memory module (12) and parity bits (PAR2) for the second data (DATA2) are written in the second partition (R4) of the first memory module (11), - in the second operating mode, further data (ED1, ED2) are written in the place of parity bits (PAR1, PAR2) in the second partition (R4, R3) of one or both the first memory module (11) and the second memory module (12).

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