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    VOLTAGE REFERENCE CIRCUIT WITH NEGATIVE LINEAR TEMPERATURE CHANGE
    1.
    发明专利
    VOLTAGE REFERENCE CIRCUIT WITH NEGATIVE LINEAR TEMPERATURE CHANGE 失效

    公开(公告)号：JPH07295667A

    公开(公告)日：1995-11-10

    申请号：JP32961594

    申请日：1994-12-02

    Applicant: CONS RIC MICROELETTRONICA ,  ST MICROELECTRONICS SRL

    Inventor： SCACCIANOCE SALVATORE ,  PALARA SERGIO ,  AIELLO NATALE

    IPC: G05F3/30

    Abstract: PURPOSE: To provide a circuit that generates a reference voltage with negative temperature coefficient together with a band gap reference voltage with positive temperature coefficient. CONSTITUTION: This circuit includes a network consisting of a Vbe voltage multiplier circuit (K'Vbe) circulating a properly stabilized current against change in a supply voltage between an output node A of an amplifier and a band gap voltage generating network, at least one resistor R connected between a band gap voltage node and ground, and resistive voltage dividers R1, R2 connected to between an output node and ground.

    LARGE-CURRENT MOS TRANSISTOR INTEGRATED BRIDGE STRUCTURE FOR OPTIMIZATION OF CONTINUITY POWER LOSS
    2.
    发明专利
    LARGE-CURRENT MOS TRANSISTOR INTEGRATED BRIDGE STRUCTURE FOR OPTIMIZATION OF CONTINUITY POWER LOSS 失效

    公开(公告)号：JPH05226597A

    公开(公告)日：1993-09-03

    申请号：JP31502492

    申请日：1992-11-25

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219

    Abstract: PURPOSE: To provide a large-current MOS transistor integrated bridge which is formed in a monolithic structure on a single Si substrate, optimizing a conduction power loss. CONSTITUTION: An N -type substrate 3, which includes at least two arms respectively comprised of first and second MOS Trs and which forms a positive potential output terminal K1, covered with an N -type epitaxial layer 4. A bridge is comprised of a P and P -type insulating regions 13, 25 and 14, 16, including N -type drain regions 15, 16, N-type drain regions 19, 20 and a pair of N -type source regions 23, 24 forming continuously P-type main body regions 21, 22 and a negative potential output terminal with respect to each of the first Tr. The bridge also consists of an N -type drain regions 5, 6, including N-type drain regions 31, 32 with respect to each of the second Tr, continuously P-type main body regions 9, 10 and a pair of N -type regions 11, 12 forming respectively corresponding ac inputs A3, A4.

    POWER SUPPLY CIRCUIT FOR REMOTELY TURNING-ON ELECTRICAL APPLIANCES
    3.
    发明申请
    POWER SUPPLY CIRCUIT FOR REMOTELY TURNING-ON ELECTRICAL APPLIANCES 审中-公开
    用于远程开关电器的电源电路

    公开(公告)号：WO2010106113A2

    公开(公告)日：2010-09-23

    申请号：PCT/EP2010053480

    申请日：2010-03-17

    Applicant: ST MICROELECTRONICS SRL ,  AIELLO NATALE

    Inventor： AIELLO NATALE

    IPC: H02M1/36

    CPC classification number: H02M1/36 ,  H02M2001/0032 ,  Y02B70/16 ,  Y10T307/826

    Abstract: A power supply circuit (30; 30'; 30'') for an electrical appliance (49), comprising a turning-on stage (32; 32') configured for determining a transition from a turned-off state, in which the power supply circuit (30; 30; 30) is off and does not supply electric power, to a turned-on state of the power supply circuit (30; 30'; 30''). The turning-on stage (32; 32') comprises a transducer (33; 36) of the remote-control type configured for triggering the transition in response to the reception of a wireless signal.

    Abstract translation: 一种用于电器（49）的电源电路（30; 30'; 30“），包括被配置用于确定从关闭状态转变的引导台（32; 32'），其中所述电源 供电电路（30; 30; 30）关闭，不向电源电路（30; 30'; 30“）的导通状态供电。 所述接通级（32; 32'）包括所述远程控制类型的换能器（33; 36），其被配置为响应于无线信号的接收而触发所述转换。

    4.
    发明专利
    未知

    公开(公告)号：IT1318952B1

    公开(公告)日：2003-09-19

    申请号：ITMI20002125

    申请日：2000-10-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： AIELLO NATALE ,  LA BARBERA ATANASIO ,  RANDAZZO VINCENZO ,  TORRISI GIOVANNI LUCA

    IPC: H05B41/285

    Abstract: An electronic thermal protection circuit is for high currents which can occur in the start-up phase in lighting converters. The circuit is associated with a power device having an output terminal connected to an electric load and at least one control terminal receiving a predetermined driving current value by a driving circuit portion. Advantageously, an integrated temperature sensor is provided to detect the temperature of the power device, and an output stage is connected downstream of the sensor to switch off the driving circuit portion when a predetermined operation temperature is exceeded.

    5.
    发明专利
    未知

    公开(公告)号：ITMI20002125D0

    公开(公告)日：2000-10-02

    申请号：ITMI20002125

    申请日：2000-10-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： AIELLO NATALE ,  LA BARBERA ATANASIO ,  RANDAZZO VINCENZO ,  TORRISI GIOVANNI LUCA

    IPC: H05B41/285

    Abstract: An electronic thermal protection circuit is for high currents which can occur in the start-up phase in lighting converters. The circuit is associated with a power device having an output terminal connected to an electric load and at least one control terminal receiving a predetermined driving current value by a driving circuit portion. Advantageously, an integrated temperature sensor is provided to detect the temperature of the power device, and an output stage is connected downstream of the sensor to switch off the driving circuit portion when a predetermined operation temperature is exceeded.

    6.
    发明专利
    未知

    公开(公告)号：DE69128936T2

    公开(公告)日：1998-07-16

    申请号：DE69128936

    申请日：1991-11-25

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PAPARO MARIO ,  AIELLO NATALE

    IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219 ,  H01L21/76

    Abstract: The structure comprises at least arms (1, 2) each formed from a first and a second MOS transistor (M3, M1; M4, M2). Its integrated monolithic construction provides for a type N++ substrate (3) forming a positive potential output terminal (K1) which is overlaid by a type N-epitaxial layer (4). For each of the first transistors (M3; M4) this comprises a type P, P+ insulating region (13, 25; 14, 26) containing a type N+ enriched drain region (15; 16), a type N drain region (19; 20) and, in succession, a type P body region (21; 22) and a pair of type N+ source regions (23; 24) forming a negative potential output terminal (A1) respectively. For each of the second transistors (M1, M2) the structure comprises a type N+ enriched drain region (5, 6) containing a type N drain region (31, 32) and in succession a type P body region (9; 10) and a pair of type N+ regions (11; 12) forming corresponding alternating current inputs (A3, A4) respectively.

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