公开(公告)号：DE69834499T2

公开(公告)日：2007-04-19

申请号：DE69834499

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMISANO GIUSEPPE ,  FERLA GIUSEPPE ,  GIRLANDO GIOVANNI

IPC: H03F1/56 ,  H03F1/22

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

公开(公告)号：DE69834499D1

公开(公告)日：2006-06-14

申请号：DE69834499

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMISANO GIUSEPPE ,  FERLA GIUSEPPE ,  GIRLANDO GIOVANNI

IPC: H03F1/56 ,  H03F1/22

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

公开(公告)号：DE69822836T2

公开(公告)日：2005-03-24

申请号：DE69822836

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FILORAMO PIETRO ,  PALMISANO GIUSEPPE ,  SALERNO RAFFAELE

IPC: H03D7/14 ,  H03D7/16 ,  H03D7/18

公开(公告)号：DE69822836D1

公开(公告)日：2004-05-06

申请号：DE69822836

申请日：1998-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FILORAMO PIETRO ,  PALMISANO GIUSEPPE ,  SALERNO RAFFAELE

IPC: H03D7/14 ,  H03D7/16 ,  H03D7/18

公开(公告)号：ITUB20155416A1

公开(公告)日：2017-05-10

申请号：ITUB20155416

申请日：2015-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： FINOCCHIARO ALESSANDRO ,  PALMISANO GIUSEPPE

IPC: H02M3/07 ,  H02M7/217

公开(公告)号：IT1398747B1

公开(公告)日：2013-03-18

申请号：ITMI20100418

申请日：2010-03-16

Applicant: ST MICROELECTRONICS SRL

Inventor： SAPONE GIUSEPPINA ,  ITALIA ALESSANDRO ,  RAGONESE EGIDIO ,  PALMISANO GIUSEPPE

公开(公告)号：ITVA20090080A1

公开(公告)日：2011-06-05

申请号：ITVA20090080

申请日：2009-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： GUERRA RANIERI ,  PALMISANO GIUSEPPE

公开(公告)号：ITTO20070563A1

公开(公告)日：2009-01-31

申请号：ITTO20070563

申请日：2007-07-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FINOCCHIARO ALESSANDRO ,  GIRLANDO GIOVANNI ,  PALMISANO GIUSEPPE

公开(公告)号：ITMI20040871A1

公开(公告)日：2004-07-30

申请号：ITMI20040871

申请日：2004-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： GIRLANDO GIOVANNI ,  MOTTA CARLA ,  PALMISANO GIUSEPPE

IPC: H03F1/22 ,  H03F3/189

公开(公告)号：DE69819677D1

公开(公告)日：2003-12-18

申请号：DE69819677

申请日：1998-02-19

Applicant: ST MICROELECTRONICS SRL

Inventor： CALI GIOVANNI ,  GRANATA ANGELO ,  PALMISANO GIUSEPPE

IPC: H03F3/72 ,  H03F3/00

Abstract: A circuit for switching a capacitor (C) in an exclusive manner, on the selected one of a plurality of integrated amplifiers (A1, A2, ... AN) comprises a first current generator (IB) connected between a first supply node (VCC) and a first node of the circuit (H), a second current generator (IC) connected between a second supply node (GND) and a second node (L) of the circuit, electrically in parallel to the capacitor (C), an array of switches (S1, S2, ..., SN) of the same number of the integrated amplifiers, exclusively switcheable on, each connecting a directly biased diode (D1, D2, ..., DN) between the first node (H) and the second node (L), each integrated amplifier having a supply node coupled to the connecting node between a respective diode and a respective connecting switch of said array.