12.
    发明专利
    未知

    公开(公告)号:ITMI20011291D0

    公开(公告)日:2001-06-19

    申请号:ITMI20011291

    申请日:2001-06-19

    Abstract: A method for automatically calibrating a phase locked loop (PLL) system includes estimating a frequency value of an input signal applied to the system. Based on the estimated frequency value, a driving signal is generated for a plurality of internal switches in the PLL system. A PLL system may also implement this automatic calibration method.

    13.
    发明专利
    未知

    公开(公告)号:DE602005012052D1

    公开(公告)日:2009-02-12

    申请号:DE602005012052

    申请日:2005-03-31

    Abstract: A digital high-pass filter (12) has an input (IN), an output (OUT), and a subtractor stage (20), having a first input terminal, a second input terminal and an output terminal. The first input terminal of the subtractor stage (20) is connected to the input (IN) of the digital high-pass filter (12) and the output terminal is connected to the output (OUT) of the digital high-pass filter (12). A recursive circuit branch (21) is connected between the output (OUT) of the digital high-pass filter (12) and the second input terminal of the subtractor stage (20). Within the recursive circuit branch (21) are cascaded an accumulation stage (23), constituted by an integrator circuit, and a divider stage (24). The cutoff frequency (f t ) of the digital high-pass filter (12) is variable according to a dividing factor (den) of the divider stage (24) .

    15.
    发明专利
    未知

    公开(公告)号:IT1315978B1

    公开(公告)日:2003-03-26

    申请号:ITRM20000425

    申请日:2000-07-31

    Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

    16.
    发明专利
    未知

    公开(公告)号:ITMI20011291A1

    公开(公告)日:2002-12-19

    申请号:ITMI20011291

    申请日:2001-06-19

    Abstract: A method for automatically calibrating a phase locked loop (PLL) system includes estimating a frequency value of an input signal applied to the system. Based on the estimated frequency value, a driving signal is generated for a plurality of internal switches in the PLL system. A PLL system may also implement this automatic calibration method.

    17.
    发明专利
    未知

    公开(公告)号:ITRM20000425D0

    公开(公告)日:2000-07-31

    申请号:ITRM20000425

    申请日:2000-07-31

    Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

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