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    Fully differential, switched capacitor, operational amplifier circuit with common-mode controlled output
    1.
    发明授权
    Fully differential, switched capacitor, operational amplifier circuit with common-mode controlled output 有权

    公开(公告)号：US6411166B2

    公开(公告)日：2002-06-25

    申请号：US86491601

    申请日：2001-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BASCHIROTTO ANDREA ,  CUSINATO PAOLO ,  MONTAGNA GIAMPIERO ,  CASTELLO RINALDO

    IPC: H03F3/00 ,  H03F3/45

    CPC classification number: H03F3/4565 ,  H03F3/005 ,  H03F3/45183

    Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

    5.
    发明专利
    未知

    公开(公告)号：DE60024246T2

    公开(公告)日：2006-08-10

    申请号：DE60024246

    申请日：2000-06-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLONNA VITTORIO ,  BASCHIROTTO ANDREA ,  CUSINATO PAOLO ,  GANDOLFI GABRIELE

    IPC: H03F3/45

    Abstract: The present invention refers to a completely differential operational amplifier of the folded cascode type. In one embodiment the completely differential operational amplifier of the folded cascode type comprises: a differential output stage (15, 16, 17, 18, 19, 20 21, 22); a differential input stage (11, 12) able to drive said output stage (15, 16, 17, 18, 19, 20 21, 22); said differential output stage (15, 16, 17, 18, 19, 20 21, 22) includes a first branch (15, 16, 17, 18) having at least a first (16) and a second (17) transistor, and a second branch (19, 20 21, 22) having at least a third (20) and a fourth (21) transistor; said first (15, 16, 17, 18) and second (19, 20 21, 22) branch are coupled to a first (VDD) and to a second (GND) feeding voltage; a feedback circuit (40) of said first (16), second (17), third (20) and fourth (21) transistors; characterized in that said feedback circuit (40) is constituted by a single amplifier (40) having four inputs (IN1, IN2, IN3, IN4) and four outputs (OUT1, OUT2, OUTS, OUT4), said four inputs (IN1, IN2, IN3, IN4) take the voltage present on a terminal (23, 13, 24, 14) of said first (16), second (17), third (20) and fourth (21) transistors, and said four outputs (OUT1, OUT2, OUT3, OUT4) provide each a voltage to the control elements of said first (16), second (17), third (20) and fourth (21) transistors, which depend on the value of the input voltage of said four inputs (IN1, IN2, IN3, IN4).

    6.
    发明专利
    未知

    公开(公告)号：DE60018557D1

    公开(公告)日：2005-04-14

    申请号：DE60018557

    申请日：2000-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GANDOLFI GABRIELE ,  BASCHIROTTO ANDREA ,  COLONNA VITTORIO ,  CUSINATO PAOLO

    IPC: H03M3/02

    Abstract: The present invention refers to a digital analogical converter comprising a sigma delta cascade modulator having two outputs, particularly a third order sigma delta modulator 2+1. In an embodiment the digital analogical converter comprises: a sigma delta modulator (1) of the type having two outputs (67, 68) able to supply a first (Y1) and a second (Y2) signal to said two outputs (67, 68); a reconstruction circuit (2) of first said (Y1) and second (Y2) signal able to provide a reconstructed signal (Yout); a filter (3) able to filter said reconstructed signal (Yout); characterized in that said reconstruction circuit (2) combines said first (Y1) and second (Y2) signals according to the following relationship Yout= Y1* (1+ Z ) - Y2* (1- Z ) + Y2* Z * (1- Z ) where Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.

    7.
    发明专利
    未知

    公开(公告)号：IT1315978B1

    公开(公告)日：2003-03-26

    申请号：ITRM20000425

    申请日：2000-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CUSINATO PAOLO ,  BASCHIROTTO ANDREA ,  PASOLINI FABIO

    IPC: H03M3/00

    Abstract: A method of re-establishing the stability of a sigma-delta modulator having a plurality of integrator stages in cascade and a quantizer, achieving very short resetting times, a bit sequence corresponding to an instability state of the modulator is defined, the bit-stream output by the modulator is monitored to check whether it includes the instability sequence and, if the instability sequence is detected, the last integrator stage is reset and one or more preceding integrator stages are reset, progressively, until the instability sequence is no longer detected.

    8.
    发明专利
    未知

    公开(公告)号：DE69529615D1

    公开(公告)日：2003-03-20

    申请号：DE69529615

    申请日：1995-11-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  CUSINATO PAOLO

    IPC: H03K3/037 ,  H03K3/356

    Abstract: A timed bistable circuit (latch) is described which includes two inverters (INV1, INV2) each having its input (Z+, Z-) connected to the output of the other, an output (U-, U+) of the circuit via a "buffer" (BF2, BF1) and an input (I+, I-) of the circuit via a controlled electronic switch (S1, S2). The supply terminals (A, B) of the inverters are connected to the supply terminals (Vdd, GND) of the circuit via another two controlled switches (S3, S4). A clock generator (CK') provides timing signals (Vck, Vck) to control both the input switches (S1, S2) to open or close and to control the supply switches (S3, S4) to close or open when the input switches (S1, S2) are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches (S5, S6) between the supply terminals (A, B) of the inverters and the supply terminals (Vdd, GND) which are controlled by a timing signal (Vckd) in such a way as to close with a predetermined delay with respect to the closure of the input switches (S1, S2) and to open when these latter open.

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