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    11.
    发明专利
    未知

    公开(公告)号：DE69821939D1

    公开(公告)日：2004-04-01

    申请号：DE69821939

    申请日：1998-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

    Abstract: The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor; growth of tunnel oxide; Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

    12.
    发明专利
    未知

    公开(公告)号：ITMI992651A1

    公开(公告)日：2001-06-20

    申请号：ITMI992651

    申请日：1999-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  PIO FEDERICO

    IPC: H01L21/8246 ,  H01L27/112

    Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

    13.
    发明专利
    未知

    公开(公告)号：ITMI991617D0

    公开(公告)日：1999-07-22

    申请号：ITMI991617

    申请日：1999-07-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLA LIBERA GIOVANNA ,  PATELMO MATTEO

    IPC: H01L27/115

    Abstract: An EEPROM cell with improved current performance, the EEPROM cell having: a selection transistor with a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, the drain region of the memory cell and said source region of the selection transistor are connected together, and the source and drain regions of the memory cell and the source and drain regions of the selection transistor share an active area with a pair of sides that linearly converge from one end to the other end

    15.
    发明专利
    未知

    公开(公告)号：IT1314143B1

    公开(公告)日：2002-12-04

    申请号：ITMI992651

    申请日：1999-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  PIO FEDERICO

    IPC: H01L21/8246 ,  H01L27/112

    Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

    16.
    发明专利
    未知

    公开(公告)号：ITMI991617A1

    公开(公告)日：2001-01-22

    申请号：ITMI991617

    申请日：1999-07-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DALLA LIBERA GIOVANNA ,  PATELMO MATTEO

    IPC: H01L27/115

    Abstract: An EEPROM cell with improved current performance, the EEPROM cell having: a selection transistor with a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, the drain region of the memory cell and said source region of the selection transistor are connected together, and the source and drain regions of the memory cell and the source and drain regions of the selection transistor share an active area with a pair of sides that linearly converge from one end to the other end

    18.
    发明专利
    未知

    公开(公告)号：ITMI992651D0

    公开(公告)日：1999-12-20

    申请号：ITMI992651

    申请日：1999-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  PIO FEDERICO

    IPC: H01L21/8246 ,  H01L27/112

    Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

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