公开(公告)号：DE602005005289T2

公开(公告)日：2009-07-09

申请号：DE602005005289

申请日：2005-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： GROSSIER NICOLAS BERNARD ,  KUMAR CHILAKALA RAVI ,  PEZZINI SAVERIO

IPC: G06F9/445

Abstract: A system for correcting errors in read-only memory devices (40) by means of memory patches, wherein patch data (30) is used as read data (60) in the place of erroneous data stored at a given location (50) in the memory (40). The system includes a processing core (PC), such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses (50) being patched. The processing core (PC) is configured for providing different patch-data (30) for correcting errors depending on whether it is performing a code access or a data access to an address (50) being patched.

公开(公告)号：DE602005005289D1

公开(公告)日：2008-04-24

申请号：DE602005005289

申请日：2005-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： GROSSIER NICOLAS BERNARD ,  KUMAR CHILAKALA RAVI ,  PEZZINI SAVERIO

IPC: G06F9/445

Abstract: A system for correcting errors in read-only memory devices (40) by means of memory patches, wherein patch data (30) is used as read data (60) in the place of erroneous data stored at a given location (50) in the memory (40). The system includes a processing core (PC), such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses (50) being patched. The processing core (PC) is configured for providing different patch-data (30) for correcting errors depending on whether it is performing a code access or a data access to an address (50) being patched.

公开(公告)号：DE60210990D1

公开(公告)日：2006-06-01

申请号：DE60210990

申请日：2002-11-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F13/26 ,  G06F13/24

公开(公告)号：DE60205106D1

公开(公告)日：2005-08-25

申请号：DE60205106

申请日：2002-08-07

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G06F13/38

Abstract: A serial interface for communicating with peripherals has circuit means for generating pointers to the single bits of words addressed in the memory sections, circuit means of serial transfer of data from or to at least a peripheral connectable to the interface, coupled to the memory and executing the configuration command pointed in the memory section for storing commands, and a relative control register coupled to the memory and to the circuit means of serial transfer, controlling the transfer of data to be transmitted or received. The interface does not require that an external controller provide configuration commands for each datum to be transmitted or received because the memory sections for storing data are divided in distinct memory spaces and each memory space is destined to store data pertaining to a respective peripheral connected to the interface, the memory section destined to store commands contains all the configuration commands of the interface for communicating with peripherals connected to it and the interface comprises an additional circuit for generating addresses to the memory section storing the configuration commands. This circuit is input with addresses provided on the external address bus and generates, in function of them, corresponding addresses at which the appropriate configuration commands to be executed are stored. A method of managing a serial peripheral interface is also disclosed.

公开(公告)号：ITVA20020057A1

公开(公告)日：2004-05-15

申请号：ITVA20020057

申请日：2002-11-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G08C20060101 ,  H03M1/10 ,  H03M1/12

公开(公告)号：DE69326329D1

公开(公告)日：1999-10-14

申请号：DE69326329

申请日：1993-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G11C17/00 ,  G06F15/78 ,  G11C16/02 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/48 ,  G11C29/50 ,  G11C16/06

Abstract: A method of directly reading the current of cells (7, 8) of a memory (3) forming part of a microcontroller (1, 1') by performing a write operation of the cells and using the existing cell programming logic. For this purpose, the programming voltage supply line (16) is supplied with a low voltage (e.g. 1 V); the word line of the cell for reading is enabled; and a write instruction of a data item presenting a predetermined logic level (e.g. zero) is performed at the bit corresponding to the cell for reading. By providing an additional pass transistor (25) connected to each reference bit line (RBL) and an additional reference cell enabling line (REF-EN), the reference cells (8) may also be read directly.

公开(公告)号：DE69314013D1

公开(公告)日：1997-10-23

申请号：DE69314013

申请日：1993-06-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PEZZINI SAVERIO

IPC: G11C5/14 ,  G06F12/16 ,  G11C16/06 ,  G11C17/00

Abstract: A protection circuit (1) comprising a first and second supply line (8, 9) at a first and second supply voltage (VCC, VPP) respectively; a reference voltage source (3); a comparator (2) connected to the first supply line (8) and the source; and a switch (30) controlled by the comparator via a control terminal and located between the second supply line (9) and the output (31) of the circuit (1). To reduce static consumption of the comparator (2) under normal operating conditions, the circuit (1) comprises enabling control elements (4-6, 29) connected to the two supply lines (8, 9) and to the comparator (2) for disabling the comparator and turning on the switch (30) when the two supply voltages differ by a value below a predetermined threshold, but are greater than a reference value.