公开(公告)号：DE602005005289D1

公开(公告)日：2008-04-24

申请号：DE602005005289

申请日：2005-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： GROSSIER NICOLAS BERNARD ,  KUMAR CHILAKALA RAVI ,  PEZZINI SAVERIO

IPC: G06F9/445

Abstract: A system for correcting errors in read-only memory devices (40) by means of memory patches, wherein patch data (30) is used as read data (60) in the place of erroneous data stored at a given location (50) in the memory (40). The system includes a processing core (PC), such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses (50) being patched. The processing core (PC) is configured for providing different patch-data (30) for correcting errors depending on whether it is performing a code access or a data access to an address (50) being patched.

公开(公告)号：DE602005005289T2

公开(公告)日：2009-07-09

申请号：DE602005005289

申请日：2005-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： GROSSIER NICOLAS BERNARD ,  KUMAR CHILAKALA RAVI ,  PEZZINI SAVERIO

IPC: G06F9/445

Abstract: A system for correcting errors in read-only memory devices (40) by means of memory patches, wherein patch data (30) is used as read data (60) in the place of erroneous data stored at a given location (50) in the memory (40). The system includes a processing core (PC), such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses (50) being patched. The processing core (PC) is configured for providing different patch-data (30) for correcting errors depending on whether it is performing a code access or a data access to an address (50) being patched.