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    4.
    发明专利
    未知

    公开(公告)号：DE602005005289D1

    公开(公告)日：2008-04-24

    申请号：DE602005005289

    申请日：2005-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GROSSIER NICOLAS BERNARD ,  KUMAR CHILAKALA RAVI ,  PEZZINI SAVERIO

    IPC: G06F9/445

    Abstract: A system for correcting errors in read-only memory devices (40) by means of memory patches, wherein patch data (30) is used as read data (60) in the place of erroneous data stored at a given location (50) in the memory (40). The system includes a processing core (PC), such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses (50) being patched. The processing core (PC) is configured for providing different patch-data (30) for correcting errors depending on whether it is performing a code access or a data access to an address (50) being patched.

    5.
    发明专利
    未知

    公开(公告)号：DE602005005289T2

    公开(公告)日：2009-07-09

    申请号：DE602005005289

    申请日：2005-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GROSSIER NICOLAS BERNARD ,  KUMAR CHILAKALA RAVI ,  PEZZINI SAVERIO

    IPC: G06F9/445

    Abstract: A system for correcting errors in read-only memory devices (40) by means of memory patches, wherein patch data (30) is used as read data (60) in the place of erroneous data stored at a given location (50) in the memory (40). The system includes a processing core (PC), such as an ARM processor, adapted to perform opcode accesses as well as data accesses to memory addresses (50) being patched. The processing core (PC) is configured for providing different patch-data (30) for correcting errors depending on whether it is performing a code access or a data access to an address (50) being patched.

    6.
    发明专利
    未知

    公开(公告)号：DE602005007851D1

    公开(公告)日：2008-08-14

    申请号：DE602005007851

    申请日：2005-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GROSSIER NICOLAS BERNARD

    IPC: G06F9/318 ,  G06F12/14

    Abstract: A system for providing controlled access to a memory area (60) storing code and data, includes a processor (110) cooperating with the memory area (60). The processor is configured for marking the instructions processed with a field describing the origin of the code being executed, and enabling data access in the memory area (60) only from authorized code. Typically, the processor (110) includes a pipeline emulation block (120), and the controlled access to said memory area (60) is implemented via the pipeline emulation block (120). The processor may be a RISC (Reduced Instruction Set Computer) processor (10), such as an ARM processor, configured for associating to the instructions currently in the pipeline (120) a bit marking if the instruction in question has been executed from an authorized memory area or not.

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