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公开(公告)号：JPH08190628A
公开(公告)日：1996-07-23
申请号：JP20877595
申请日：1995-08-16
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PENNINO LAURA , MANCUSO MASSIMO , TRAVAGLIA FEDERICO , POLUZZI RINALDO , RIZZOTTO GIANGUIDO
Abstract: PROBLEM TO BE SOLVED: To perform an excellent noise reduction operation while preserving useful high-pass (high band) information. SOLUTION: This device is provided with an interface 1 for obtaining the gray levels of the pixel to be processed of images and the adjacent pixel, a difference circuit 2 for generating the difference of the gray levels of the pixel to be processed and the adjacent pixel, a fuzzy flat area smoothing circuit 8 for performing the low-pass (low band) smoothing of an almost uniform area stipulated by the pixel and the adjacent pixel, an edge preservation smoothing circuit 9 for performing a low-pass filtering processing to a high frequency information area stipulated by the pixel and the adjacent pixel, an area voter circuit 4 for supplying a measurement value for examining whether or not the area stipulated by the pixel and the adjacent pixel is almost uniform and a soft switching circuit 10 for weighting the output of the smoothing circuits 8 and 9 based on the measurement value.
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公开(公告)号：JPH08102873A
公开(公告)日：1996-04-16
申请号：JP10261495
申请日：1995-04-26
Applicant: CONS RIC MICROELETTRONICA , ST MICROELECTRONICS SRL
Inventor： MANCUSO MASSIMO , POLUZZI RINALDO , RIZZOTTO GIANGUIDO
Abstract: PURPOSE: To reduce noise of a television signal and also perform simultaneous scan conversion by including a noise reducing circuit and a simultaneous scan conversion circuit of a TV signal. CONSTITUTION: A filter archtecture is provided with at least one filter 3 which has plural digital inputs Pi and X that receive television signal elements through an interface and also has a few outputs NR and includes at least one interpolating block which takes a result of a filtering operation for noise that is associated with a television signal by the outputs NR, is connected to an input in the filter 3, also operates in fuzzy theory and executes scan conversion of a television signal that should be presented to other outputs SRC of the filter 3.
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公开(公告)号：JPH0869526A
公开(公告)日：1996-03-12
申请号：JP3357595
申请日：1995-02-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MANUSO MASSIMO , POLUZZI RINALDO , RIZZOTTO GIANGUIDO
Abstract: PURPOSE: To obtain the inexpensive filter with a simple structure by which noise is reduced and an image ridge is emphasized. CONSTITUTION: The filter 1 is provided with an image ridge detection circuit 6 connected between outputs of the 1st and 2nd processing circuit means 2, 3 and with an image ridge emphasis circuit 7 connected between the output of the image ridge detection circuit and a noise reduction circuit 5 in addition to the 1st and 2nd processing circuit means 2, 3 receiving a digital image signal, a noise detection circuit 4, the noise reduction circuit 5 and an output of the image ridge emphasis circuit 7 is an output of the filter 1.
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公开(公告)号：JPH07143455A
公开(公告)日：1995-06-02
申请号：JP13627294
申请日：1994-05-26
Applicant: ST MICROELECTRONICS SRL
Inventor： SCALISE FABIO , POLUZZI RINALDO
IPC: H04N7/015
Abstract: PURPOSE: To reduce the hardware silicon area of a video image decoder by reducing the amount of memory lines and, at the same time, to improve the modularity of the decoder. CONSTITUTION: A video image decoder incorporates channels (J and L), their corresponding processing blocks 13 and 14 and a demultiplexer 12 which receives TV signals from transmission channels (J and L) so as to individually process signals from the channels (J and L). A video image decoder for implementing a processing algorithm in a 40-ms mode on a high-resolution TV receiver of a type suitable for processing TV signals received on the corresponding transmission channels (J and L) and the signal processing method of the decoder can be obtained.
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公开(公告)号：DE69727911D1
公开(公告)日：2004-04-08
申请号：DE69727911
申请日：1997-04-24
Applicant: ST MICROELECTRONICS SRL
Inventor： MANCUSO MASSIMO , POLUZZI RINALDO , D ALTO VIVIANA , MOLINARI LUCA
Abstract: A method and a device for motion estimated and compensated Field Rate Up-conversion (FRU) for video applications, providing for: a) dividing an image field to be interpolated into a plurality of image blocks (IB), each image block made up of a respective set of image elements of the image field to be interpolated; b) for each image block (K(x,y)) of at least a sub-plurality (Q1,Q2) of said plurality of image blocks, considering a group of neighboring image blocks (NBÄ1Ü-NBÄ4Ü); c) determining an estimated motion vector for said image block (K(x,y)), describing the movement of said image block (K(x,y)) from a previous image field to a following image field between which the image field to be interpolated is comprised, on the basis of predictor motion vectors (PÄ1Ü-PÄ4Ü) associated to said group of neighboring image blocks; d) determining each image element of said image block (K(x,y)) by interpolation of two corresponding image elements in said previous and following image fields related by said estimated motion vector. Step c) provides for: c1) applying to the image block (K(x,y)) each of said predictor motion vectors to determine a respective pair of corresponding image blocks in said previous and following image fields, respectively; c2) for each of said pairs of corresponding image blocks, evaluating an error function (errÄiÜ) which is the Sum of luminance Absolute Difference (SAD) between corresponding image elements in said pair of corresponding image blocks; c3) for each pair of said predictor motion vectors, evaluating a degree of homogeneity (H(i,j)); c4) for each pair of said predictor motion vectors, applying a fuzzy rule having an activation level (rÄkÜ) which is higher the higher the degree of homogeneity of the pair of predictor motion vectors and the smaller the error functions of the pair of predictor motion vectors; c5) determining an optimum fuzzy rule having the highest activation level (rÄoptÜ), and determining the best predictor motion vector (PÄminÜ) of the pair associated to said optimum fuzzy rule having the smaller error function; c6) determining the estimated motion vector for said image block (K(x,y)) on the basis of said best predictor motion vector (PÄminÜ).
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Patent Agency Ranking
公开(公告)号：DE69724412D1
公开(公告)日：2003-10-02
申请号：DE69724412
申请日：1997-05-12
Applicant: ST MICROELECTRONICS SRL
Inventor： MANCUSO MASSIMO , D ALTO VIVIANA , SIRTORI DANIELE , POLUZZI RINALDO
Abstract: The level of Gaussian noise in a memory field being scanned by rows is reduced by reconstructing each pixel by fuzzy logic processors, the latter processing the the values of pixels neighbouring the pixel being processed and belonging to a processing window defined by the last scanned row and the row being scanned, thus minimizing the memory requisite of the filtering system to a single row. The system perform an adaptive filtering within the current field itself and does not produce @ edge-smoothing @ effects as in prior adaptive filtering systems operating on consecutive fields.
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公开(公告)号：DE69721790D1
公开(公告)日：2003-06-12
申请号：DE69721790
申请日：1997-12-30
Applicant: ST MICROELECTRONICS SRL
Inventor： COLLA FEDERICA , MANCUSO MASSIMO , POLUZZI RINALDO
Abstract: A digital image color correction device employing fuzzy logic, for correcting a facial tone image portion of a digital video image, characterized in that it comprises: a pixel fuzzifier unit (1) receiving in input a stream of pixels belonging to a sequence of correlated frames of a digital video image and computing a multi level value representing a membership of each pixel to a skin color class; a global parameter estimator (2) receiving in input each of said pixel and the relative membership value, and computing a first and a second parameter which define the characteristics of a portion of said image that belongs to said skin color class; a processing unit (3) connected downstream to said global parameter estimator and to said pixel fuzzifier unit and adapted to correct each of the pixels of said portion of the image that belongs to said skin color class, according to said first global parameter (300), to obtain corrected pixels; and a processing switch (4) for outputting said pixels or said corrected pixels according to said second global parameter (400).
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公开(公告)号：DE69528351D1
公开(公告)日：2002-10-31
申请号：DE69528351
申请日：1995-04-28
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUNO DARIO , POLUZZI RINALDO , MANARESI NICOLO , FRANCHI ELEONORA
Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form. It comprises a storage section (MEM) having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals (PP) on such outputs; the storage section (MEM) is input a plurality of supply voltage signals (VI) and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs. Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches (SW) controlled by storage elements (E) are used in the storage section (MEM).
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公开(公告)号：DE69522313D1
公开(公告)日：2001-09-27
申请号：DE69522313
申请日：1995-04-28
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： BRUNO DARIO , POLUZZI RINALDO , MANARESI NICOLO , FRANCHI ELEONORA
Abstract: The analog processor of this invention can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry. To achieve this independence, the processor is basically implemented and integrated with MOS transistors, has both voltage inputs (AI) and outputs (OUT), and includes a biasing section (BIAS) which supplies voltage bias signals (VG), of which at least one is substantially the sum of a voltage proportional to the threshold voltage of the MOS transistors and a reference voltage. This reference voltage can be extracted from a reference potential which is stable to temperature and process parameters, for example that produced by a bandgap type of generator. A major feature of the processor according to the invention is the linearity of its input-output characteristic relative to that reference voltage. It follows that it may be advantageous to extract that reference voltage by division from a signal indicating the width of the input signal variation range, thereby to achieve compensation for or independence of variations of this range.
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公开(公告)号：DE69329332T2
公开(公告)日：2001-02-22
申请号：DE69329332
申请日：1993-05-26
Applicant: ST MICROELECTRONICS SRL
Inventor： SCALISE FABIO , POLUZZI RINALDO
Abstract: A video image decoder architecture for implementing a processing algorithm in the 40-ms mode on high-resolution TV sets, of a kind adapted to handle TV signals being received on respective transmission channels (A,C), comprises: a video signal demultiplexer (12) being input said transmission channels (A,C); respective processing blocks (13,14) for separately handling the signals from each of the channels (A,C) and comprising, a video image format converter (15), a local memory (17) connected after the converter, and at least one median filter (25) and one systolic filter (27) cascade connected after said memory for restoring, by interpolation, signal samples related to successive lines of the video image;and a summing node (11) for adding together the outputs from each processing block (13,14) by obtaining a time mean between restored samples (Ai,Ci) of the channels (A,C). This architecture allows a drastic reduction in the number of memories required for processing the restore algorithm, as well as a reduction in overall silicon area for the system, and accordingly, the possibility of having the whole 40-millisecond processing portion integrated to a single chip.
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