公开(公告)号：DE69528351D1

公开(公告)日：2002-10-31

申请号：DE69528351

申请日：1995-04-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  POLUZZI RINALDO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G05F3/24 ,  G06N7/04 ,  G06G7/60

Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form. It comprises a storage section (MEM) having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals (PP) on such outputs; the storage section (MEM) is input a plurality of supply voltage signals (VI) and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs. Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches (SW) controlled by storage elements (E) are used in the storage section (MEM).

公开(公告)号：DE69522313D1

公开(公告)日：2001-09-27

申请号：DE69522313

申请日：1995-04-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  POLUZZI RINALDO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G06N7/04 ,  G06G7/60

Abstract: The analog processor of this invention can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry. To achieve this independence, the processor is basically implemented and integrated with MOS transistors, has both voltage inputs (AI) and outputs (OUT), and includes a biasing section (BIAS) which supplies voltage bias signals (VG), of which at least one is substantially the sum of a voltage proportional to the threshold voltage of the MOS transistors and a reference voltage. This reference voltage can be extracted from a reference potential which is stable to temperature and process parameters, for example that produced by a bandgap type of generator. A major feature of the processor according to the invention is the linearity of its input-output characteristic relative to that reference voltage. It follows that it may be advantageous to extract that reference voltage by division from a signal indicating the width of the input signal variation range, thereby to achieve compensation for or independence of variations of this range.

公开(公告)号：DE69522313T2

公开(公告)日：2002-04-18

申请号：DE69522313

申请日：1995-04-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  POLUZZI RINALDO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G06N7/04 ,  G06G7/60

Abstract: The analog processor of this invention can carry out processings independently of the operating temperature and process parameters, in a reliable manner and at high performance levels using fairly simple circuitry. To achieve this independence, the processor is basically implemented and integrated with MOS transistors, has both voltage inputs (AI) and outputs (OUT), and includes a biasing section (BIAS) which supplies voltage bias signals (VG), of which at least one is substantially the sum of a voltage proportional to the threshold voltage of the MOS transistors and a reference voltage. This reference voltage can be extracted from a reference potential which is stable to temperature and process parameters, for example that produced by a bandgap type of generator. A major feature of the processor according to the invention is the linearity of its input-output characteristic relative to that reference voltage. It follows that it may be advantageous to extract that reference voltage by division from a signal indicating the width of the input signal variation range, thereby to achieve compensation for or independence of variations of this range.

公开(公告)号：DE69418206D1

公开(公告)日：1999-06-02

申请号：DE69418206

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G05F3/24 ,  G05F3/26

公开(公告)号：DE69534914D1

公开(公告)日：2006-05-18

申请号：DE69534914

申请日：1995-01-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： GIACALONE BIAGIO ,  BRUNO DARIO ,  MATRANGA VINCENZO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G05F3/24 ,  G05F3/26 ,  H03F3/30

Abstract: The present level shift circuit has a first (I1) and a second (I2) input respectively for input of a first and a second voltage signal and an output (OT) and comprises: a) a first transistor (Q1) having a control terminal (G1), a first (S1) and a second (D1) main conduction terminal identifying a main conduction path, and b) a second transistor (Q2) of the same type as said first transistor (Q1) and having a control terminal (G2), a first (S2) and a second (D2) main conduction terminal identifying a main conduction path. The first signal is applied essentially between said control terminal (G1) and said first terminal (S1) of said first transistor (Q1) and said second input (I2) is coupled with the control terminal (G2) of said second transistor (Q2). The currents flowing in the conduction paths of the first (Q1) and the second (Q2) transistors are mutually proportional and one made from the other. The output (OT) is coupled with the first terminal (S2) of the second transistor (Q2). The control terminal (G1) of said first transistor (Q1) is connected to a potential reference (GND). The first signal is applied essentially to said first terminal (S1) of said first transistor (Q1).

公开(公告)号：DE69434039T2

公开(公告)日：2006-02-23

申请号：DE69434039

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  GNUDI ANTONIO

IPC: G05F3/24 ,  G05F3/26

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal, b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents, c) a voltage generator (VG) connected between said two control terminals (G1, G2), and d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals. The output (OT) is coupled to one (G2) of said control terminals.

公开(公告)号：DE69418206T2

公开(公告)日：1999-08-19

申请号：DE69418206

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  FRANCHI ELEONORA

IPC: G05F3/24 ,  G05F3/26

公开(公告)号：DE69434039D1

公开(公告)日：2004-11-04

申请号：DE69434039

申请日：1994-12-30

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO ,  GNUDI ANTONIO

IPC: G05F3/24 ,  G05F3/26

Abstract: The transistor threshold extraction circuit in accordance with the present invention has an output (OT) and comprises: a) at least two transistors (M1, M2) of the same type having respectively two control terminals (G1, G2) and having essentially the same threshold with each of said two transistors (M1, M2) also having a first (S1, S2) and a second (D1, D2) main conduction terminal, b) a current mirror (MC) having at least two input-output terminals (IM, OM) with said two terminals (IM, OM) coupled respectively to said two transistors (M1, M2) so as to supply to them the bias currents, c) a voltage generator (VG) connected between said two control terminals (G1, G2), and d) a feedback path (FP) between said control terminals (G1, G2) and one (OM) of said input-output terminals. The output (OT) is coupled to one (G2) of said control terminals.

公开(公告)号：DE69424171T2

公开(公告)日：2001-03-01

申请号：DE69424171

申请日：1994-10-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO

IPC: G06G7/12 ,  G05F3/24 ,  G06N7/04 ,  G06G7/26

Abstract: Analog processor (2) of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators (3) of membership function (FA) each having an output (4) supplying a value corresponding to a degree of truth complemented to one ( alpha ') of logical assignments of the type (A is A') with the outputs (4) being connected together to form a common circuit node (7) and also connected to a current generator (9) and the processor (2) comprising also a voltage control device (5) inserted between a supply voltage pole (VD) and a ground voltage reference (GND) and a one-way element (8) connected to the common circuit node (7) and the one-way element (8) having an output (10) producing an overall degree of truth ( OMEGA ) for the antecedent part of the fuzzy rule to be processed.

公开(公告)号：DE69424171D1

公开(公告)日：2000-05-31

申请号：DE69424171

申请日：1994-10-31

Applicant: CONS RIC MICROELETTRONICA

Inventor： BRUNO DARIO ,  GIACALONE BIAGIO ,  MANARESI NICOLO

IPC: G06G7/12 ,  G05F3/24 ,  G06N7/04 ,  G06G7/26

Abstract: Analog processor (2) of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators (3) of membership function (FA) each having an output (4) supplying a value corresponding to a degree of truth complemented to one ( alpha ') of logical assignments of the type (A is A') with the outputs (4) being connected together to form a common circuit node (7) and also connected to a current generator (9) and the processor (2) comprising also a voltage control device (5) inserted between a supply voltage pole (VD) and a ground voltage reference (GND) and a one-way element (8) connected to the common circuit node (7) and the one-way element (8) having an output (10) producing an overall degree of truth ( OMEGA ) for the antecedent part of the fuzzy rule to be processed.