公开(公告)号：ITMI20001804D0

公开(公告)日：2000-08-02

申请号：ITMI20001804

申请日：2000-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PIERLUIGI ,  PASOTTI MARCO ,  GUATINI GIOVANNI

IPC: G06F1/26

Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.

公开(公告)号：DE60117676D1

公开(公告)日：2006-05-04

申请号：DE60117676

申请日：2001-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： NAVONI LORIS GIUSEPPE ,  BORGATTI MICHELE ,  CALI LORENZO ,  ROLANDI PIERLUIGI

IPC: G06F9/445 ,  G06F8/61

Abstract: The invention relates to a method of expanding the functional capabilities of portable electronic devices with user friendly modes, wherein a host device is associated a quick-connect function-expanding module. In this method, at each installation of a given module, the functional expansion module and the host device recognize each other; on first installation of a given module in the host device, a series of checking operations are carried out automatically; the user can select to activate the available expansion; and once a given application is selected, the configuration and functions required for each application are stored.

公开(公告)号：IT1319614B1

公开(公告)日：2003-10-20

申请号：ITMI20002807

申请日：2000-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

IPC: G11C8/08 ,  G11C16/12

公开(公告)号：IT1318318B1

公开(公告)日：2003-07-28

申请号：ITMI20001804

申请日：2000-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PIERLUIGI ,  GUATINI GIOVANNI ,  PASOTTI MARCO

IPC: G06F1/26

Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.

公开(公告)号：ITMI20001804A1

公开(公告)日：2002-02-04

申请号：ITMI20001804

申请日：2000-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PIERLUIGI ,  PASOTTI MARCO ,  GUATINI GIOVANNI

IPC: G06F1/26

Abstract: An electronic circuit for controlling voltage signals at particular critical nodes of an electronic device connected to the circuit, said circuit being inserted between a supply voltage reference and a ground voltage reference, and having at least one internal reference node connected to the critical nodes, and including at least one capacitive element inserted between the supply voltage reference and the ground voltage reference, and connected to the internal reference node through a charging device, said capacitive element being charged with the supply voltage reference to maintain, at the internal reference node, a voltage value above a predetermined threshold voltage as the supply voltage reference is cut off.

公开(公告)号：ITRM20010525D0

公开(公告)日：2001-08-30

申请号：ITRM20010525

申请日：2001-08-30

Applicant: ST MICROELECTRONICS SRL

Inventor： GUAITINI GIOVANNI ,  PASOTTI MARCO ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

IPC: G11C16/08 ,  G11C16/16

Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.