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    1.
    发明专利
    未知

    公开(公告)号：DE60041199D1

    公开(公告)日：2009-02-05

    申请号：DE60041199

    申请日：2000-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  DE SANDRE GUIDO ,  GUAITINI GIOVANNI ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

    Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

    3.
    发明专利
    未知

    公开(公告)号：DE60134870D1

    公开(公告)日：2008-08-28

    申请号：DE60134870

    申请日：2001-12-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  POLES MARCO ,  IEZZI DAVID ,  PASOTTI MARCO

    IPC: G11C11/56

    Abstract: The invention relates to a programming method of a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), the method comprising at least a step of writing a logic value in the multilevel memory cell by setting one of the programming levels (LA) thereof, these levels being included in the plurality of levels (N), with respect to a reference level (LR) according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value (Lmax) for the levels (LS, LR) is reached. The invention relates also to a multilevel memory device comprising a plurality of multilevel memory cells organised into sectors, split into a plurality of data units (UD) whereon a programming operation is performed in parallel according to the method of the invention.

    6.
    发明专利
    未知

    公开(公告)号：DE60102203D1

    公开(公告)日：2004-04-08

    申请号：DE60102203

    申请日：2001-12-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANI ,  IEZZI DAVID ,  POLES MARCO

    IPC: G11C11/56

    Abstract: It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m-1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m-1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

    7.
    发明专利
    未知

    公开(公告)号：ITRM20010525A1

    公开(公告)日：2003-02-28

    申请号：ITRM20010525

    申请日：2001-08-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  PASOTTI MARCO ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

    IPC: G11C16/08 ,  G11C16/16

    Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

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