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    2.
    发明专利
    未知

    公开(公告)号：ITRM20010525A1

    公开(公告)日：2003-02-28

    申请号：ITRM20010525

    申请日：2001-08-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  PASOTTI MARCO ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

    IPC: G11C16/08 ,  G11C16/16

    Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

    4.
    发明专利
    未知

    公开(公告)号：ITTO990944A1

    公开(公告)日：2001-04-30

    申请号：ITTO990944

    申请日：1999-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C11/56 ,  G11C16/28

    Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

    5.
    发明专利
    未知

    公开(公告)号：ITMI990859A1

    公开(公告)日：2000-10-23

    申请号：ITMI990859

    申请日：1999-04-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C16/16

    Abstract: A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.

    9.
    发明专利
    未知

    公开(公告)号：IT1312471B1

    公开(公告)日：2002-04-17

    申请号：ITMI991017

    申请日：1999-05-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C11/56 ,  G11C16/34

    Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

    10.
    发明专利
    未知

    公开(公告)号：ITMI20000832A1

    公开(公告)日：2001-10-15

    申请号：ITMI20000832

    申请日：2000-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI ,  ROCCHI ALESSANDRO ,  BISIO MARCO ,  DE SANDRE GUIDO ,  PASOTTI MARCO

    IPC: G01R31/28

    Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

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