Abstract:
PROBLEM TO BE SOLVED: To provide a controlled erasing method in a flash EEPROM device which does not require structural change of memory. SOLUTION: A controlled erasing method comprises at least a step (40) of supplying at least one erase pulse to cell of memory array, a step of comparing a threshold value voltage of cell erased with a certain lower threshold value, a step of performing selectively soft programming to the erased cell having the threshold value voltage lower than the lower threshold value voltage and a step (42) of verifying that the erased cell has the threshold value higher than the lower threshold value. When the erased cells of the predetermined number, which is at least one, have the threshold value higher than the first threshold value, only one erase pulse is given to all cells (44), and the selective soft programming and verify step are repeated.
Abstract:
Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.
Abstract:
For each cell (1) to be programmed, the present threshold value (Vo) of the cell is determined; the desired threshold value (VTAR) is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse (S) is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells (1) of a memory array (2) which is connected to a single word line (51) and to different bit lines (41 - 4N), each with a programming pulse (S1 - SN) the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.
Abstract:
A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
Abstract:
The invention relates to a method of expanding the functional capabilities of portable electronic devices with user friendly modes, wherein a host device is associated a quick-connect function-expanding module. In this method, at each installation of a given module, the functional expansion module and the host device recognize each other; on first installation of a given module in the host device, a series of checking operations are carried out automatically; the user can select to activate the available expansion; and once a given application is selected, the configuration and functions required for each application are stored.