中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.029 seconds)

    12.
    发明专利
    未知

    公开(公告)号：DE60226987D1

    公开(公告)日：2008-07-17

    申请号：DE60226987

    申请日：2002-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CRIPPA LUCA ,  RAGONE GIANCARLO

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/12

    Abstract: The present invention relates to a method and an electronic device for stabilising the voltage on the drain terminals of multilevel non volatile memory cells (3) in the programming step. In the method the application of said voltage is provided through a drain voltage regulator (2) having an output (OUT) connected to said terminals in a common circuit node (A) by means of a metal line (4) conduction path having a parasitic intrinsic resistance (Rpars). Advantageously, a feedback path (5) is provided between the node (A) and an input of the regulator (2).

    13.
    发明专利
    未知

    公开(公告)号：ITMI990722A1

    公开(公告)日：2000-10-09

    申请号：ITMI990722

    申请日：1999-04-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G05F3/30

    Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

    14.
    发明专利
    未知

    公开(公告)号：IT1313878B1

    公开(公告)日：2002-09-24

    申请号：ITMI992624

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G11C11/56

    Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

    17.
    发明专利
    未知

    公开(公告)号：IT1312244B1

    公开(公告)日：2002-04-09

    申请号：ITMI990722

    申请日：1999-04-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G05F3/30

    Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

    18.
    发明专利
    未知

    公开(公告)号：ITMI992624D0

    公开(公告)日：1999-12-17

    申请号：ITMI992624

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G11C11/56

    Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

Patent Agency Ranking