中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.026 seconds)

    READ CIRCUIT FOR NONVOLATILE MEMORY
    1.
    发明专利
    READ CIRCUIT FOR NONVOLATILE MEMORY 失效

    公开(公告)号：JP2001084782A

    公开(公告)日：2001-03-30

    申请号：JP2000253119

    申请日：2000-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  CRIPPA LUCA

    IPC: G11C16/06 ,  G11C16/28

    Abstract: PROBLEM TO BE SOLVED: To eliminate the drawback that reduction of read time is limited at a low supply voltage. SOLUTION: A read circuit 1' comprises an array branch 6 having an input array node 22 connected, via an array bit line 8, to an array cell 10; a reference branch 12 having an input reference node 32 connected, via a reference bit line 14, to a reference cell 16; a current-to-voltage converter 18 connected to an output array node 56 of the array branch and to an output reference node of the reference branch to supply on both nodes 56, 58 the respective electric potentials VM, VR correlated to the currents flowing in both cells 10, 16; and a comparator 19 connected at input to both nodes 56, 58 and supplying as output a signal OUT indicative of the contents stored in the array memory cell 10; and an array decoupling stage 80 arranged between both array nodes 22, 56 to decouple both array nodes 22, 56 from one another.

    2.
    发明专利
    未知

    公开(公告)号：DE602006009662D1

    公开(公告)日：2009-11-19

    申请号：DE602006009662

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： MICHELONI RINO ,  CRIPPA LUCA ,  RAVASIO ROBERTO ,  PIO FEDERICO

    IPC: G11C16/34

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    5.
    发明专利
    未知

    公开(公告)号：DE602005012682D1

    公开(公告)日：2009-03-26

    申请号：DE602005012682

    申请日：2005-07-22

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

    Inventor： CRIPPA LUCA ,  MISSIROLI CHIARA ,  MICHELONI RINO

    IPC: G11C16/26 ,  G11C16/04

    Abstract: A reading method of a NAND memory device including the steps of: first connecting a first end terminal (12a) of a stack (12) of cells (3, 3', 3") to a reference line (13); second connecting a second end terminal (12b) of the stack (12) of cells (3, 3', 3") to a respective bitline (10); charging the bitline (10) to a predetermined bitline read voltage (V DR ), wherein one of the steps of first connecting and second connecting is carried out before charging the bitline (10) and the other of the steps of first connecting and second connecting is carried out after charging the bitline (10). An order of carrying out the steps of first connecting and second connecting is determined based on an address (MSB; AL2) of a selected cell (3', 3") .

    6.
    发明专利
    未知

    公开(公告)号：DE60226987D1

    公开(公告)日：2008-07-17

    申请号：DE60226987

    申请日：2002-12-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CRIPPA LUCA ,  RAGONE GIANCARLO

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/12

    Abstract: The present invention relates to a method and an electronic device for stabilising the voltage on the drain terminals of multilevel non volatile memory cells (3) in the programming step. In the method the application of said voltage is provided through a drain voltage regulator (2) having an output (OUT) connected to said terminals in a common circuit node (A) by means of a metal line (4) conduction path having a parasitic intrinsic resistance (Rpars). Advantageously, a feedback path (5) is provided between the node (A) and an input of the regulator (2).

    7.
    发明专利
    未知

    公开(公告)号：ITMI990722A1

    公开(公告)日：2000-10-09

    申请号：ITMI990722

    申请日：1999-04-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G05F3/30

    Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

    9.
    发明专利
    未知

    公开(公告)号：IT1313878B1

    公开(公告)日：2002-09-24

    申请号：ITMI992624

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G11C11/56

    Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

Patent Agency Ranking