公开(公告)号：EP0875905A1

公开(公告)日：1998-11-04

申请号：EP97830194.3

申请日：1997-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  De Santi, Giorgio ,  Crisenza, Giuseppe

IPC: H01B3/30 ,  C08F292/00 ,  H01L23/532

CPC classification number: H01B3/30 ,  C08F292/00 ,  H01L23/5329 ,  H01L2924/0002 ,  Y02P20/544 ,  H01L2924/00

Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is composed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

Abstract translation: 的绝缘膜之间层叠导电，通过该集成电路的互连实现，是由在其上的有机单体的无机氧化物的气凝胶的下为惰性的离子轰击已嫁接并先后在气凝胶进一步并入层以填充至少部分的 无机气凝胶的孔隙率。 复合电介质材料是热稳定的并且具有令人满意的热预算。 气凝胶电影的形成的方法，包括走上随后在纺丝室中进行超临界溶剂提取的晶片的前体化合物溶液的纺丝。

公开(公告)号：EP1772773A1

公开(公告)日：2007-04-11

申请号：EP05425698.7

申请日：2005-10-06

Applicant: STMicroelectronics S.r.l.

Inventor： Mascolo, Danilo ,  Cerofolini, Gianfranco

IPC: G03F7/00 ,  H01L27/10

CPC classification number: H01L21/32139 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  G03F7/0017 ,  H01L27/10 ,  Y10S438/946 ,  Y10S438/947 ,  Y10S977/887 ,  Y10S977/888

Abstract: The present invention relates to a method for realising a multispacer structure (1) comprising an array (3) of spacers (2) having same height, comprising the steps of:
a) realising, on a substrate (A), a sacrificial layer (4) of a predetermined first material;
b) realising, on the sacrificial layer (4), a sequence of mask spacers (5, 6) obtained by means of S n PT, which are alternatively obtained in at least two different materials;
c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer (4);
d) chemically and/or anisotropically etching the predetermined first material with selective removal of the exposed portions of the sacrificial layer (4);
e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure (1).

Abstract translation: 本发明涉及一种方法，用于实伊辛（1）包括阵列（3）的间隔件（2）具有相同的高度，其包括以下步骤的一个multispacer结构：1）真实伊辛，在基板（A），一个牺牲层（ 4）在预定的第一材料制成; b）中实伊辛，牺牲层（4），掩模间隔物的（一个序列5上，6）由S n中PT，其是在至少两个不同的材料可替代地获得来获得; c）中化学蚀刻以选择性地去除该蚀刻材料和牺牲层的部分曝光的掩模间隔物的两种不同的材料中的一个（4）; D）化学和/或各向异性蚀刻以选择性地去除所述牺牲层的暴露部分的预定第一材料（4）; E）化学蚀刻以选择性地去除multispacer结构（1）的这个被蚀刻材料和取得的掩模间隔物的两种不同的材料中的另一个。

公开(公告)号：EP1742226A1

公开(公告)日：2007-01-10

申请号：EP05425489.1

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  Mascolo, Danilo

IPC: G11C13/02 ,  H01L21/768 ,  B82B3/00

CPC classification number: H01L21/76816 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/70916 ,  G11C2213/81 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: The invention relates to a method for realising an electric connection in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components, comprising the steps of:
a) providing, above a semiconductor substrate (A), a seed (6) having at least a notched wall (7) substantially perpendicular to the substrate (A), which is crossed by n recesses placed at a distance bo from one another and having depth a n ≥(n-1)t sp +a 0 and width b n =2t si +2(n-1)t sp ;
b) realising, from the seed (6) by means of S n PT, n conductive nanowires (2) of thickness t si alternated with insulating nanowires (3) of thickness (t sp -t si ) wherein t sp is the width of a pair of consecutive conductive (2) and insulating (3) nanowires, so as to obtain, at each realisation of a conductive nanowire (2) of a given order, the filling or the completion of the filling of a recess (8) of the same order by means of a respective elbow-like portion (2a) of the conductive nanowire (2), and the partial filling together with the conductive (2) and insulating (3) nanowires of lower order already realised, of the recesses (8) of greater order by means of respective portions with notched profile (2b; 3b) and formation of the nanometric circuit architecture.
c) realising, above the nanometric circuit architecture, an insulating layer (9);
d) opening, on the insulating layer, n windows (10), each window (10) being open essentially in correspondence with a respective recess (8), with exposure of at least part of an elbow-like portion (2a) of a conductive nanowire (2) present in said recess (8).
e) realising, above the insulating layer (9), n conductive dies (4) addressed towards the standard electronic components, each die (4) overlapping in correspondence with a respective window (10) to a respective exposed part of the elbow-like portion (2a) of a conductive nanowire (2) with obtainment of n contacts (5) realising the electric connection.

Abstract translation: 本发明涉及一种用于纳米电路结构和标准电子部件之间的半导体电子器件的电连接的真实伊辛的方法，包括以下步骤：a）提供，上述的半导体基板（A），具有在种子（6） 至少一个凹口的壁（7）基本垂直于所述基体（A），这是通过在彼此的距离柏摆放着n凹槽交叉，并具有‰¥（N-1）T SP的深度+ a 0和宽度BN = 2吨SI 2（N-1）T SP; b）中实伊辛，从种子（6）由S n中PT的手段，N导电纳米线（2）厚度t SI的交替有绝缘纳米线（3）厚度的（T SP -t SI）worin吨SP是的宽度 一对连续的导电的（2）和绝缘（3）纳米线，以获得在给定顺序的导电纳米线（2）的每个实现，填充或一个凹部的填充完成（8）的 相同的顺序由导电纳米线（2）的一个respectivement肘状部（2a）的平均值，并与导电的（2）和部分填充一起绝缘（3）较低阶的纳米线已经实现了凹部，（ 通过respectivement部的方式与凹口的轮廓（图2b，3b）的与形成所述纳米电路结构的更大的顺序的8）。 c）中实伊辛，所述纳米电路结构的上方，（在绝缘层9）; D）开口，在绝缘层上，N个窗口（10），每个窗口（10）被打开基本上与respectivement凹部（8）对应，具有一个肘状部（2a）的至少一部分的曝光 导电纳米线（2）存在于所述凹部（8）。 E）实伊辛，绝缘层（9）的上方，N导电此（4）朝向所述标准电子元件寻址，每个（4）对应于一个respectivement窗口（10），以一个respectivement重叠露出的一部分肘状 在导电性纳米线（2）中n触头（5）实伊辛的电连接的获得的部分（2a）中。

公开(公告)号：EP1278234A2

公开(公告)日：2003-01-22

申请号：EP01127923.9

申请日：2001-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Cerofolini, Gianfranco ,  Ferla, Giuseppe

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/312

CPC classification number: H01L21/28167 ,  H01L29/51

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer (3) formed between two silicon plates (1,2), and wherein the silicon plates (1,2) overhang the oxide layer (3) all around to define an undercut (5) having a substantially rectangular cross-sectional shape.
The method comprises the steps of:

chemically altering the surfaces of the silicon plates (1,2) to have different functional groups (6,7) provided in the undercut (5) from those in the remainder of the surfaces; and
selectively reacting the functional groups (6,7) provided in the undercut (5) with an organic molecule (8) having a reversibly reducible center and a molecular length substantially equal to the width of the undercut (5), thereby to establish a covalent bond to each end of the organic molecule (8).

Abstract translation: 公开了一种通过电介质栅极氧化物制造具有可控和可调制传导路径的MOS晶体管的方法，其中晶体管结构包括形成在两个硅板（1,2）之间的电介质氧化物层（3），并且其中硅板 （1,2）围绕所述氧化物层（3）突出以限定具有基本上矩形横截面形状的底切（5）。 该方法包括以下步骤：化学改变硅板（1,2）的表面以具有设置在底切（5）中的不同的官能团（6,7）与其余表面中的那些; 选择性地使底切（5）中提供的官能团（6,7）与具有可逆可还原中心和分子长度基本上等于底切（5）的宽度的有机分子（8）反应，从而建立 与有机分子（8）的每个末端共价键。