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    Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material and method of fabrication
    1.
    发明公开
    Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material and method of fabrication 失效
    具有无机气凝胶的低介电常数集成电路用有机填料复合膜接枝无机材料和其生产

    公开(公告)号：EP0875905A1

    公开(公告)日：1998-11-04

    申请号：EP97830194.3

    申请日：1997-04-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cerofolini, Gianfranco ,  De Santi, Giorgio ,  Crisenza, Giuseppe

    IPC: H01B3/30 ,  C08F292/00 ,  H01L23/532

    CPC classification number: H01B3/30 ,  C08F292/00 ,  H01L23/5329 ,  H01L2924/0002 ,  Y02P20/544 ,  H01L2924/00

    Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is composed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

    Abstract translation: 的绝缘膜之间层叠导电，通过该集成电路的互连实现，是由在其上的有机单体的无机氧化物的气凝胶的下为惰性的离子轰击已嫁接并先后在气凝胶进一步并入层以填充至少部分的 无机气凝胶的孔隙率。 复合电介质材料是热稳定的并且具有令人满意的热预算。 气凝胶电影的形成的方法，包括走上随后在纺丝室中进行超临界溶剂提取的晶片的前体化合物溶液的纺丝。

    Process of final passivation of integrated circuit devices
    2.
    发明公开
    Process of final passivation of integrated circuit devices 失效
    Verfahren zur abschliessenden Passivierung integrierter Schaltungen

    公开(公告)号：EP1387394A3

    公开(公告)日：2004-04-07

    申请号：EP03077997.9

    申请日：1997-04-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Santi, Giorgio ,  Zanotti, Luca ,  Crisenza, Giuseppe

    IPC: H01L23/31 ,  H01L21/3105

    CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process of final passivation of an integrated circuit device comprising at least one integrated circuit chip, comprising a step of formation of a layer of protective material (5) over a top surface of the at least one integrated circuit (3, 3', 3"), characterized in that said layer of protective material (5) comprises a High-Density Plasma Chemical Vapor Deposition (HDPCVD) and by providing for a subsequent step of planarization of said layer of protective material (5) to obtain a protection layer having a substantially flat top surface. (Figures 1 and 2).

    Abstract translation: 包括至少一个集成电路芯片的集成电路器件的最终钝化过程，包括在所述至少一个集成电路（3,3'，3'）的顶表面上形成保护材料层（5）的步骤 “），其特征在于，所述保护材料层（5）包括高密度等离子体化学气相沉积（HDPCVD），并且通过提供所述保护材料层（5）的平面化的随后步骤，以获得具有 （图1和2）。

    Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof
    3.
    发明公开
    Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof 有权
    集成电阻元件，其具有用于其制备这样的电阻元件和过程的相变存储器元件

    公开(公告)号：EP1331675A1

    公开(公告)日：2003-07-30

    申请号：EP02425013.6

    申请日：2002-01-17

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Zonca, Romina ,  Marangon, Maria Santina ,  De Santi, Giorgio

    IPC: H01L45/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    Abstract: A vertical-current-flow resistive element (12) comprising a monolithic region (12) having a first portion (12a) and a second portion (12b) arranged on top of one another and formed by a single material. The first portion has a first resistivity, and the second portion (12b) has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion (12a) is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion (12a) than in the second portion (12b). Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi 2 , Ta, WSi, and the increase in resistivity is obtained by nitridation.

    Abstract translation: 的垂直电流流电阻元件（12）包括具有第一部分（12a）和（12b）的布置在彼此的顶部上，并通过一个单一的材料形成的第二部分的单片区域（12）。 所述第一部分具有第一电阻率，并且所述第二部分（12b）具有第二电阻率，比所述第一电阻率。 为了这个目的，具有均匀的电阻率和高度比其他尺寸首先形成的至少一个大的整体区域; 然后所述第一部分（12a）的电阻率是通过引入，从顶部增加，物种确实形成具有单片区域的导电材料的普遍地共价键，所以没有所述物质的浓度变得在第一部分更高（12A ）比（在第二部分12b）。 优选地，导电材料是二元或三元合金，从TiAl金属，的TiSi2，钽，的WSi选自，和电阻率的增加是由氮化获得。

    Process of final passivation of integrated circuit devices
    7.
    发明公开
    Process of final passivation of integrated circuit devices 失效
    集成电路器件的最终钝化过程

    公开(公告)号：EP1387394A2

    公开(公告)日：2004-02-04

    申请号：EP03077997.9

    申请日：1997-04-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Santi, Giorgio ,  Zanotti, Luca ,  Crisenza, Giuseppe

    IPC: H01L21/3105

    CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process of final passivation of an integrated circuit device comprising at least one integrated circuit chip, comprising a step of formation of a layer of protective material (5) over a top surface of the at least one integrated circuit (3, 3', 3"), characterized in that said layer of protective material (5) comprises a High-Density Plasma Chemical Vapor Deposition (HDPCVD) and by providing for a subsequent step of planarization of said layer of protective material (5) to obtain a protection layer having a substantially flat top surface. (Figures 1 and 2).

    Abstract translation: 一种包括至少一个集成电路芯片的集成电路器件的最终钝化过程，包括在至少一个集成电路（3,3'，3）的顶表面上形成保护材料层（5）的步骤， “），其特征在于，所述保护材料层（5）包括高密度等离子体化学气相沉积（HDPCVD）并且通过提供所述保护材料层（5）的平坦化的后续步骤以获得具有 基本平坦的顶面（图1和2）。

    Process of final passivation of integrated circuit devices
    9.
    发明公开
    Process of final passivation of integrated circuit devices 失效
    Verfahren zur abschliessenden Passivierung integrierter Schaltungen

    公开(公告)号：EP0887847A1

    公开(公告)日：1998-12-30

    申请号：EP97830173.7

    申请日：1997-04-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Santi, Giorgio ,  Crisenza, Giuseppe ,  Zanotti, Luca

    IPC: H01L21/3105 ,  H01L21/98

    CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31055 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process of final passivation of an integrated circuit device comprising at least one integrated circuit chip (3;3',3''), comprising a step of formation of a layer of protective material (5) over a top surface of the at least one integrated circuit, characterized by providing for a subsequent step of planarization of said layer of protective material (5) to obtain a protection layer having a substantially flat top surface.

    Abstract translation: 包括至少一个集成电路芯片（3; 3'，3“）的集成电路器件的最终钝化过程，包括在所述至少一个顶表面上形成保护材料层（5）的步骤 一个集成电路，其特征在于提供所述保护材料层（5）的平面化的随后步骤，以获得具有基本平坦的顶表面的保护层。

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