公开(公告)号：EP0948050A1

公开(公告)日：1999-10-06

申请号：EP98830172.7

申请日：1998-03-24

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Feruccio ,  Percolla, Giuseppe ,  Fragapane, Leonardo

IPC: H01L27/02 ,  H01L23/485

CPC classification number: H01L29/7808 ,  H01L23/62 ,  H01L24/05 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The device comprises a chip of semiconductor material (10), a plate (14) of insulating material on the chip, a conducting strip of doped semiconductor material which has a portion (15) which extends over the plate (14), a portion (16) of a layer of semiconductor material which extends over the plate (14) and contains active regions and a metallic element (17) which is in contact with the portion (15) of conducting strip which extends over the plate (14) and has an area (20) designed to be used for electrical connection to a terminal, outside the chip, of the electronic device. To increase the useful area of the chip, the metallic element (17) extends in large part over the portion (16) of the layer of semiconductor material containing active regions, and is separated from this portion (16) by a layer of insulating material.

Abstract translation: 该器件包括半导体材料芯片（10），芯片上的绝缘材料板（14），掺杂半导体材料的导电条，其具有在板（14）上延伸的部分（15），部分 在所述板（14）上延伸并且包含有源区域的金属元件（17），所述金属元件（17）与所述板（14）上延伸的导电条的所述部分（15）接触并具有 设计用于与芯片外的终端电连接的电子设备的区域（20）。 为了增加芯片的有用面积，金属元件（17）大部分地延伸在含有活性区域的半导体材料层的部分（16）上，并且通过绝缘材料层与该部分（16）分离 。

公开(公告)号：EP0865085A1

公开(公告)日：1998-09-16

申请号：EP97830108.3

申请日：1997-03-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fragapane, Leonardo

IPC: H01L29/739 ,  H01L29/10

CPC classification number: H01L29/1095 ,  H01L29/0696 ,  H01L29/7395

Abstract: An Insulated Gate Bipolar Transistor comprises a semiconductor substrate (1) of a first conductivity type forming a first electrode (C) of the device, a semiconductor layer (3) of a second conductivity type superimposed over said substrate (1), a plurality of body regions (4) of the first conductivity type formed in the semiconductor layer (3), a first doped region (7) of the second conductivity type formed inside each body region (4), an insulated gate layer (8,9) superimposed over portions of the semiconductor layer (3) between the body regions (4) and forming a control electrode of the device, a conductive layer (11) insulatively disposed over the insulated gate layer (8,9) and contacting each body region (4) and each doped region (7) formed therein, the conductive layer (11) forming a second electrode (E) of the device. In said portions of the semiconductor layer (3) between the body regions (4) second doped regions (12) of the first conductivity type are formed, and openings are provided in the insulated gate layer (8,9) at said second doped regions (12) to allow the conductive layer (11) to contact the second doped regions (12).

Abstract translation: 绝缘栅双极晶体管包括形成器件的第一电极（C）的第一导电类型的半导体衬底（1），叠加在所述衬底（1）上的第二导电类型的半导体层（3），多个 在半导体层（3）中形成的第一导电类型的主体区域（4），形成在每个体区域（4）内的第二导电类型的第一掺杂区域（7），叠置的绝缘栅极层（8,9） 在所述主体区域（4）之间的半导体层（3）的部分上方并形成所述器件的控制电极，绝缘地设置在绝缘栅极层（8,9）上并与每个体区域（4）接触的导电层（11） ）和其中形成的每个掺杂区（7），所述导电层（11）形成该器件的第二电极（E）。 在主体区域（4）的半导体层（3）的所述部分中，形成第一导电类型的第二掺杂区域（12），并且在所述第二掺杂区域的绝缘栅极层（8,9）中设置开口 （12）以允许导电层（11）接触第二掺杂区域（12）。

公开(公告)号：EP2924734B1

公开(公告)日：2018-11-28

申请号：EP15161793.3

申请日：2015-03-30

Applicant: STMicroelectronics S.r.l.

Inventor： Fragapane, Leonardo ,  Alessandria, Antonino

IPC: H01L27/08 ,  H01L27/06 ,  H01L27/07 ,  H01L29/868 ,  H01L29/78 ,  H01L29/36 ,  H01L29/43 ,  H01L29/06

CPC classification number: H01L29/868 ,  H01L27/0629 ,  H01L27/0664 ,  H01L27/0694 ,  H01L27/0727 ,  H01L27/0814 ,  H01L29/0692 ,  H01L29/36 ,  H01L29/43 ,  H01L29/66136 ,  H01L29/7804

Abstract: A diode (100; 200) is proposed. The diode is integrated on a chip (105) of semiconductor material having an anode surface (105a) and a cathode surface (105c) opposite to each other. The diode comprises at least one cathode region (120) having a doping of a first type, the cathode region extending from the cathode surface in the chip. Furthermore, the diode comprises an intrinsic region (130) having a doping of the first type with a dopant concentration lower than a dopant concentration of the cathode region, the intrinsic region extending between the anode surface and the cathode region. In addition, the diode comprises a plurality of anode regions (135c, 135f) having a doping of a second type, each anode region extending from the anode surface in the intrinsic region. The diode further comprises a cathode electrode (110) of electrically conductive material electrically coupled with said at least one cathode region on the cathode surface, and an anode electrode (115) of electrically conducting material. In the solution according to an embodiment of the present disclosure, one or more contacted anode regions (135c) of said anode regions are electrically coupled with the anode electrode on the anode surface, and one or more floating anode regions (135f) of said anode regions are electrically insulated from the anode electrode. The diode is configured so that charge carriers are injected from said at least one floating anode region into the intrinsic region in response to the applying of a control voltage between the anode electrode and the cathode electrode exceeding a threshold voltage of the diode.

公开(公告)号：EP1536463A1

公开(公告)日：2005-06-01

申请号：EP03425765.9

申请日：2003-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandria, Antonino Sebastiano ,  Fragapane, Leonardo

IPC: H01L21/331 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/7397

Abstract: A method is described for manufacturing a power device (15) with insulated trench-gate (18), integrated on a semiconductor substrate (1), providing at least the steps of:

□ realising at least a body region (4) in the semiconductor substrate (1);
□ realising a surface source region (6) on the body region (4);
□ etching the semiconductor substrate (1) and forming a trench (17) to realise the trench-gate structure (18).
The method provides the further step of:

□ forming a deep portion (6a) of the source region (6) along the trench (17).
A semiconductor power device (15) with insulated gate and trench-gate structure (18) is also described.
Advantageously, the method comprises the further step of:

□ forming a deep body portion (4a) along said trench extending deeper than the deep source portion (6a).

Abstract translation: 描述了一种方法用于集成在一个半导体衬底（1）一种制造功率器件（15）与绝缘沟槽栅极（18），提供至少如下步骤：真实伊辛至少一个主体区（4）在该半导体基板 （1）; 在主体区域实现表面源区（6）（4）; 蚀刻所述半导体基板（1）和形成沟槽（17），以实现该沟槽栅结构（18）。 该方法提供的进一步的步骤：形成沿着所述沟槽（17）的源极区域（6）的深部（6A）。 因此描述了一种半导体功率器件（15）具有绝缘栅和沟槽栅结构（18）。 有利地，该方法还包括以下步骤：形成沿着所述沟槽延伸到比深源极部分（6a）的深的深体部（4A）。

公开(公告)号：EP1469523A1

公开(公告)日：2004-10-20

申请号：EP03425242.9

申请日：2003-04-18

Applicant: STMicroelectronics S.r.l.

Inventor： Fragapane, Leonardo ,  Alessandria, Antonino

IPC: H01L29/739 ,  H01L27/07 ,  H01L27/02

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L27/0788 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/7395

Abstract: A junction device including at least a first type semiconductor region (33) and a a second type semiconductor region a(34), which are arranged contiguous to one another and have a first and, respectively, a second type of conductivity, which are opposite to one another, and a first and a second biasing region (37, 38); the device is moreover provided with a resistive region (35), which has the first type of conductivity and extends from the first type semiconductor region (33) and is contiguous to the second type semiconductor region (34) so as to form a resistive path between the first and the second biasing regions (37, 38).

Abstract translation: 甲结器件，包括至少一个第一型半导体区域（33）和aa第二型半导体区域（34）被布置邻接彼此和具有第一和分别的第二型导电性的，这是相反的 彼此，以及第一和第二偏置区域（37，38）; 该装置更上方设置有阻性区域（35），其具有第一导电类型并与所述第一型半导体区域（33）延伸，并邻接所述第二型半导体区域（34），以便形成一个电阻路径 第一和第二偏置区域（37，38）之间。

公开(公告)号：EP1022785A1

公开(公告)日：2000-07-26

申请号：EP99830023.0

申请日：1999-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： Fragapane, Leonardo

IPC: H01L29/739 ,  H01L29/10 ,  H01L27/06

CPC classification number: H01L29/1095 ,  H01L27/0611 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00

Abstract: The device, an IGBT, is formed on a chip (9) of silicon consisting of a P type substrate (10) with an N type epitaxial layer (11) which contains a first P type region (13) and a termination structure. This structure comprises a first P type termination region (14) which surrounds the first region (13), a first electrode (18) in contact with the first termination region (14) and a second electrode (21) shaped in the form of a frame close to the edge of the chip and connected to a third electrode (17) in contact with the bottom of the chip. A fourth electrode made in one piece with the first electrode (18) is in contact with the first region (13). To produce an integrated diode with good electrical characteristics connected in reverse conduction between the power terminals of the IGBT, the termination structure also comprises a fifth electrode (30), in contact with the epitaxial layer (11) along a path parallel to the edge of the first termination region (14), connected to the second electrode (21), a second P type termination region (32) which surrounds the fifth electrode (30) and a sixth electrode (33), in contact with the second termination region (32), connected to the first electrode (18).

Abstract translation: 器件IGBT是形成在由包含第一P型区域（13）和端接结构的N型外延层（11）的P型衬底（10）构成的硅芯片（9）上。 该结构包括围绕第一区域（13）的第一P型端接区域（14），与第一端接区域（14）接触的第一电极（18）和形成为第一区域 框架靠近芯片的边缘并且连接到与芯片的底部接触的第三电极（17）。 与第一电极（18）一体制成的第四电极与第一区域（13）接触。 为了产生具有良好的电特性的集成二极管，其在IGBT的功率端之间被反向导通，所述端接结构还包括与外延层（11）接触的第五电极（30），该第五电极沿平行于 连接到第二电极（21）的第一端接区域（14），围绕第五电极（30）的第二P型端接区域（32）和与第二端接区域接触的第六电极（33） 32），连接到第一电极（18）。

公开(公告)号：EP0860947A1

公开(公告)日：1998-08-26

申请号：EP97830072.1

申请日：1997-02-19

Applicant: STMicroelectronics S.r.l.

Inventor： Fragapane, Leonardo ,  Letor, Romeo

IPC: H03K17/082

CPC classification number: H03K17/0822 ,  H03K17/0828

Abstract: A fast operating, electronic protection device (1) against overvoltages, intended for a power transistor (M1) having at least one control terminal (G) of the MOS type, is of the type which comprises a Zener diode (Z1) associated with the power transistor (M1) and integrated together therewith in a semiconductor substrate (9), and comprises a second transistor (M2) connected to the power transistor into a Darlington configuration and connected, in turn, to the Zener diode (Z1).
The protection from overvoltages provided by the device (1) is very fast in operation, and can be implemented in integrated form at reduced cost and without introducing parasitic elements.

Abstract translation: 一种快速操作，电子保护装置（1）过电压，意为具有MOS型中的至少一个控制端子（G）的功率晶体管（M1），是包含与所述相关联的齐纳二极管（Z1）的类型的 功率晶体管（M1）中，用在半导体衬底（9）集成在一起存在，并且包括连接到功率晶体管成达林顿结构​​和连接，又将第二晶体管（M2），与齐纳二极管（Z1）。 从由所述设备（1）提供过电压保护是非常快的在外科手术中，并且可以在以降低的成本集成的形式和在不引入寄生元件来实现。