公开(公告)号：EP1455397A3

公开(公告)日：2005-08-17

申请号：EP03029916.8

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).
The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps: realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and realising an enrichment region (9) in the JFET area below the thicker layer.

公开(公告)号：EP1455397A2

公开(公告)日：2004-09-08

申请号：EP03029916.8

申请日：2003-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Feruccio ,  Ferla, Giuseppe ,  Camalleri, Marco

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66712

Abstract: The invention relates to a vertical-conduction and planar-structure MOS device having a double thickness of gate oxide comprising

a first portion (5a) of gate oxide having a lower thickness in a channel area close to the active areas (4), and a second portion (5b) of thicker gate oxide in a central area (11) on a JFET area and
an enrichment region (9) in the JFET area under the second . portion (5b) of thicker gate oxide (11).

The invention also relates to a method for realising on a semiconductor substrate (2) MOS transistor electronic devices (1) with improved static and dynamic performances and high scaling down density, these transistors having traditional active areas (4) defined in the substrate (2) at the periphery of a channel region whereon a gate region is realised. The method provides at least the following steps:

realising the MOS transistor starting from a planar structure with a double thickness of gate oxide comprising a thin layer in the channel area close to the active areas (4) and a thicker layer in the central area (11) on the channel; and
realising an enrichment region (9) in the JFET area below the thicker layer.

Abstract translation: 本发明涉及一种垂直导电和平面结构MOS器件，其具有栅极氧化物的双重厚度，其包括在接近有源区（4）的沟道区中具有较低厚度的栅极氧化物的第一部分（5a） 在JFET区域上的中心区域（11）中较厚的栅极氧化物的第二部分（5b）和第二部分的JFET区域中的富集区域（9）。 较厚栅极氧化物（11）的部分（5b）。 本发明还涉及一种在具有改进的静态和动态性能以及高缩小密度的半导体衬底（2）MOS晶体管电子器件（1）上实现的方法，这些晶体管具有传统的有源区域（4） 在实现栅极区域的沟道区域的周围的衬底（2）。 该方法至少提供以下步骤：从具有双重厚度的栅极氧化物的平面结构开始实现MOS晶体管，该栅极氧化物在靠近有源区域（4）的沟道区域中具有薄层，并且在中心区域中具有较厚层（ 11）在频道上 并且在较厚层下面的JFET区域中实现富集区域（9）。

公开(公告)号：EP0948050A1

公开(公告)日：1999-10-06

申请号：EP98830172.7

申请日：1998-03-24

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Feruccio ,  Percolla, Giuseppe ,  Fragapane, Leonardo

IPC: H01L27/02 ,  H01L23/485

CPC classification number: H01L29/7808 ,  H01L23/62 ,  H01L24/05 ,  H01L29/4238 ,  H01L29/7811 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The device comprises a chip of semiconductor material (10), a plate (14) of insulating material on the chip, a conducting strip of doped semiconductor material which has a portion (15) which extends over the plate (14), a portion (16) of a layer of semiconductor material which extends over the plate (14) and contains active regions and a metallic element (17) which is in contact with the portion (15) of conducting strip which extends over the plate (14) and has an area (20) designed to be used for electrical connection to a terminal, outside the chip, of the electronic device. To increase the useful area of the chip, the metallic element (17) extends in large part over the portion (16) of the layer of semiconductor material containing active regions, and is separated from this portion (16) by a layer of insulating material.

Abstract translation: 该器件包括半导体材料芯片（10），芯片上的绝缘材料板（14），掺杂半导体材料的导电条，其具有在板（14）上延伸的部分（15），部分 在所述板（14）上延伸并且包含有源区域的金属元件（17），所述金属元件（17）与所述板（14）上延伸的导电条的所述部分（15）接触并具有 设计用于与芯片外的终端电连接的电子设备的区域（20）。 为了增加芯片的有用面积，金属元件（17）大部分地延伸在含有活性区域的半导体材料层的部分（16）上，并且通过绝缘材料层与该部分（16）分离 。