公开(公告)号：EP3098720A1

公开(公告)日：2016-11-30

申请号：EP15202773.6

申请日：2015-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  CONDORELLI, Riccardo ,  DISTEFANO, Gaetano

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F13/4027 ,  G06F13/4291

Abstract: A serial protocol interface in a communication device (MD) exchanging data (MOSI, MISO) over a communication link (121, 122, 123) is operated by:
- sending output data (MOSI) on (122) the communication link, and
- receiving input data (MISO) on (121) the communication link, these input data (MISO) being synchronous with a clock signal (SCK, SCLK) generated at the communication device (MD) and propagated (123) over the communication link (121, 122, 123),
- initializing operation by exchanging data over the communication link (121, 122, 123) by sending output data (MOSI) on the communication link (122) at a first data rate,
- detecting a signal transition in the input data (MISO) received on the communication link (121), and
- once such a transition is detected, exchanging data over the communication link (121, 122, 123) at a second data rate, higher than the first data, with the exchanging of data at a second data rate synchronized (18) as a function of said signal transition.

Abstract translation: 通过通信链路（121,122,123）交换数据（MOSI，MISO）的通信设备（MD）中的串行协议接口通过以下操作： - 在（122）通信链路上发送输出数据（MOSI），以及 - 在（121）通信链路上接收输入数据（MISO），这些输入数据（MISO）与在通信设备（MD）处生成并在通信链路（121）上传播（123）的时钟信号（SCK，SCLK）同步 ，122,123）， - 通过在所述通信链路（122）上以第一数据速率发送输出数据（MOSI），通过所述通信链路（121,122,123）交换数据来初始化操作， - 检测所述通信链路 在所述通信链路（121）上接收的输入数据（MISO），以及 - 一旦检测到所述转换，则以比所述第一数据高的第二数据速率在所述通信链路（121,122,123）上交换数据， 以作为所述信号转换的函数的第二数据速率交换数据（18）。

公开(公告)号：EP4102335A1

公开(公告)日：2022-12-14

申请号：EP22305741.5

申请日：2022-05-19

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  TUDOSE, Andrei ,  CLERICI, Francesco ,  BUTTA', Pasquale

IPC: G05F1/46 ,  G06F1/26

Abstract: A circuit (10), such as a microcontroller unit, MCU for instance, comprises a first node (VBAT) configured to be brought to a first voltage such as the supply voltage from a battery (LB), a second node (VDDIO) configured to be coupled (180) with an electrically powered device (ED) such as an external memory to provide electrical supply power thereto, and a voltage regulator (100) such as a LDO regulator embedded in the circuit (10) intermediate the first node (VBAT) and the second node (VDDIO). The voltage regulator (100) is activatable in a first, startup mode during which the voltage regulator (100) applies to the second node (VDDIO), and thus to the external device (ED), a voltage increasing towards a supply threshold (160). The circuit (10) comprises control circuitry (20) activatable (16, 160, vdig_en, 22) in response to the voltage at the second node (VDDIO) reaching the supply threshold (160) to bring the voltage regulator (100) to a second mode of operation (1008) wherein a programmable regulated voltage higher than the supply threshold is applied to the second node (VDDIO). The circuit (100) is configured (162) to receive low-power operation requests (1010) and, in response to low-power operation requests (1010) received, to deactivate a first high-drive regulator circuitry (102) in the voltage regulator (100) and activate a second low-power regulator circuitry (104) thus providing a third, low-power mode of operation of the circuit (10).

公开(公告)号：EP3702886A1

公开(公告)日：2020-09-02

申请号：EP20157715.2

申请日：2020-02-17

Applicant: STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  BUTTA', Pasquale

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  H02M1/00

Abstract: A method for managing the power supply in an electronic circuit comprising a processing system (11; 11'), in particular a general purpose microcontroller or a System-on-Chip or a subsystem thereof, with a radio-frequency embedded circuit (12),
said processing system (11; 11') comprising
at least a processing core (30, V12I, VI2O) and a first power regulation module (111') supplying a first regulated voltage (V12) to said processing core (30),
said radio frequency embedded circuit (12) comprising a second power regulation module (121) supplying a second regulated voltage (V reg ) to circuits (122) of the radio-frequency embedded circuit including a radio frequency transceiving portion (124), said second power regulation module (122) comprising a switched-mode power supply (1211) and generating a second regulated voltage (V reg ),
said method comprising coupling said second regulated voltage (V reg ) as voltage input of said first power regulation module (1111), said first power regulation module (1111) which generates as an output a respective first regulated voltage (V regm ) for said processing core (30),
controlling said second power regulation module (121) to operate according to a plurality of operation modes (LP1, LP2, A1, A2, LP3, LP4) including
one or more sleep modes (LP1, LP2) in which both the DC-DC converter (1211) and the second linear regulator (121) are off and
one or more active modes (A1, A2) in which both the DC-DC converter (1211) and the second linear regulator (121) are on,
wherein said second power regulation module (122) comprises a second linear regulator (1212) and
said plurality of modes (LP1, LP2, A1, A2, LP3, LP4) includes
a first further sleep mode (LP3) in which the switched-mode power supply (1211) is off and the second linear regulator (1212) is on and
a second further sleep mode in which the switched-mode power supply (1211) is on and the second linear regulator (1212) is off.

公开(公告)号：EP3141871A1

公开(公告)日：2017-03-15

申请号：EP16162411.9

申请日：2016-03-24

Applicant: STMicroelectronics S.r.l.

Inventor： CONDORELLI, Riccardo ,  MANGANO, Daniele

IPC: G01D5/20 ,  H03K17/95

CPC classification number: G01R27/26 ,  G01D5/20 ,  H03K17/9537 ,  H03K17/954

Abstract: In one embodiment, an inductive/LC sensor device includes:
- energy accumulation means (C ref ) for accumulating excitation energy,
- an LC sensor (10) configured for oscillating energized by energy accumulated,
- an energy detector (12) for detecting the energy accumulated on the energy accumulation means (C ref ) reaching a charge threshold, and
- at least one switch (S1, S2) coupled with the energy detector (12) for terminating accumulating excitation energy for the sensor (10) on the energy accumulation means (C ref ) when the charge threshold is detected having been reached by the energy detector (12).

Abstract translation: 在一个实施例中，电感/ LC传感器装置包括： - 用于累积激发能量的能量累积装置（C ref）， - 被配置为通过积聚的能量振荡激励的LC传感器（10）， - 能量检测器（12） 能量累积装置（C ref）上累积的能量达到电荷阈值;以及 - 与所述能量检测器（12）耦合的至少一个开关（S1，S2），用于终止所述传感器（10）对能量积累的累积激发能量 当检测到能量检测器（12）已经达到充电阈值时，装置（C ref）。

公开(公告)号：EP3098722A1

公开(公告)日：2016-11-30

申请号：EP15198048.9

申请日：2015-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： ROSSELLI, Salvatore Marco ,  MANGANO, Daniele ,  CONDORELLI, Riccardo

IPC: G06F15/78

CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

Abstract: A digital circuit including combinational (10) and sequential (12) circuit elements is operable to selectively (14, VRAM_M) switch at least part (12a, 120) of the circuit elements (12) to operation as random access memory.

Abstract translation: 一种数字电路，其包括组合（10）和顺序（12）的电路元件可操作以选择性地将所述电路元件（12）操作，随机存取存储器（14 VRAM_M）开关的至少一部分（12A，120）。

公开(公告)号：EP3059865A1

公开(公告)日：2016-08-24

申请号：EP15195224.9

申请日：2015-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  CONDORELLI, Riccardo

IPC: H03L1/00 ,  G06F1/14

CPC classification number: G06F1/12 ,  G06F1/14 ,  G06F1/3243 ,  H03L1/00 ,  Y02D10/152

Abstract: A clock generator in apparatus such as e.g. a microcontroller unit is calibrated by aligning at subsequent calibration times the frequency of a first clock (106) with respect to the frequency of a second clock (108) having a higher frequency accuracy than said first clock (106), with the frequency of the first clock (106) which h varies between subsequent calibration times. The frequency of the first clock (106) is aligned to a frequency which is offset by a certain amount with respect to the frequency of the second clock (108) in order counter frequency error which may accumulate over time due to the variation in the frequency of the first clock (106).

Abstract translation: 时钟发生器，例如装置中的时钟发生器。 通过在随后的校准时间对第一时钟（106）的频率相对于具有比所述第一时钟（106）更高的频率精度的第二时钟（108）的频率进行校准，来校准微控制器单元，频率为 第一时钟（106），其在随后的校准时间之间变化。 第一时钟（106）的频率对应于相对于第二时钟（108）的频率偏移一定量的频率，以便随着频率变化而随时间累积的计数器频率误差 的第一时钟（106）。

公开(公告)号：EP2966410A1

公开(公告)日：2016-01-13

申请号：EP15175313.4

申请日：2015-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： CONDORELLI, Riccardo ,  MANGANO, Daniele

IPC: G01D3/028

CPC classification number: G01R35/005 ,  G01D3/028 ,  G01D5/24 ,  G01R27/02 ,  G01R27/2605 ,  G01R35/00 ,  H02J7/045 ,  H02J7/345

Abstract: A method of interfacing a LC sensor (10) with a control unit (20) is described. Specifically, the control unit comprises a first (202) and a second (204) contact, wherein the LC sensor (10) is connected between the first (202) and the second (204) contact, and wherein a capacitor (C1) is connected between the first contact (202) and a ground (GND).
In particular, in order to start the oscillation of the LC sensor, the method comprising the steps of:
- during a first phase, connecting the first contact (202) to a supply voltage (VDD) and placing the second contact (204) in a high impedance state, such that the capacitor (C1) is charged through the supply voltage (VDD);
- during a second phase (2004), placing the first contact (202) in a high impedance state and connecting the second contact (204) to the ground (GND), such that the capacitor (C1) transfers charge towards the LC sensor (10); and
- during a third phase (2006), placing the first contact (202) and the second contact (204) in a high impedance state, such that the LC sensor (10) is able to oscillate.

Abstract translation: 描述了将LC传感器（10）与控制单元（20）接口连接的方法。 具体地，控制单元包括第一触点（202）和第二触点（204），其中LC传感器（10）连接在第一触点（202）和第二触点（204）之间，并且其中电容器（C1） 连接在第一触点（202）和地（GND）之间。 具体地，为了开始LC传感器的振荡，该方法包括以下步骤： - 在第一阶段期间，将第一触点（202）连接至电源电压（VDD）并将第二触点（204）置于 高阻抗状态，使得电容器（C1）通过电源电压（VDD）充电; - 在第二阶段（2004）期​​间，将第一触点（202）置于高阻抗状态并将第二触点（204）连接至地（GND），使得电容器（C1）将电荷转移至LC传感器 10）; 和 - 在第三阶段（2006）期间，将第一触点（202）和第二触点（204）置于高阻抗状态，使得LC传感器（10）能够振荡。

公开(公告)号：EP2026493A1

公开(公告)日：2009-02-18

申请号：EP07114463.8

申请日：2007-08-16

Applicant: STMicroelectronics S.r.l.

Inventor： MANGANO, Daniele ,  GUARNACCIA, Giuseppe ,  PISTRITTO, Carmelo

IPC: H04L7/02 ,  G06F1/12 ,  G06F13/40 ,  G06F5/06

CPC classification number: H04L7/02 ,  H04L7/0008 ,  H04L7/005

Abstract: Full-duplex communication over a communication link between an initiator (IN, NI) operating with an initiator clock (IP CLK) and a target (TA, R) operating with a target clock (NoC CLK) involves, in communication from the initiator (IN, NI) to the target (TA, R) the steps of:
- storing data from the initiator (IN, NI) in a first FIFO memory (320) with the initiator clock (IP CLK),
- reading (324) data from the initiator (IN, NI) stored in the first FIFO memory (320), wherein reading is with the target clock (Noc CLK')
- transmitting (12, 18, 24) the data read from the first FIFO memory (320) over a first mesochronous link (19), and
- storing (28) the data transmitted over the first mesochronous link (19) in a buffer (26) whereby said data are made available to the target (TA, R).
Communication from the target (TA, R) to the initiator (IN, NI) includes the steps of:
- transmitting (14, 22, 28) data from the target (TA, R) over a second mesochronous link (29), and
- storing (18, 344) the data transmitted (14, 22, 28) over the second mesochronous link (29) in a second FIFO memory (340), wherein storing is with the target clock (NoC CLK'), whereby the data are made available to said initiator (IN, NI) for reading from the second FIFO memory (340) with the initiator clock signal (IP CLK).

Abstract translation: 通过以起始时钟（IP CLK）操作的发起者（IN，NI）与以目标时钟（NoC CLK）操作的目标（TA，R）之间的通信链路的全双工通信涉及从发起者（ IN，NI）到目标（TA，R）的步骤： - 将来自发起者（IN，NI）的数据存储在具有启动器时钟（IP CLK）的第一FIFO存储器（320）中， - 读取（324）数据 存储在第一FIFO存储器（320）中的发起者（IN，NI），其中读取与从第一FIFO存储器（320）读取的数据的目标时钟（Noc CLK'） - 发送（12,18,24） 通过第一中间同步链路（19），以及 - 将（28）通过第一中间同步链路（19）发送的数据存储在缓冲器（26）中，由此所述数据对目标（TA，R）可用。 从目标（TA，R）到发起者（IN，NI）的通信包括以下步骤： - 通过第二中间同步链路（29）从目标（TA，R）传输（14,22,28）数据，以及 - 在第二FIFO存储器（340）中存储（18,344）在第二中间同步链路（29）上发送的数据（14,22,28），其中存储与目标时钟（NoC CLK'），由此数据 对于所述启动器（IN，NI）可用于利用发起者时钟信号（IP CLK）从第二FIFO存储器（340）读取。