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    Digital system with an output buffer with a switching current settable to load-independent constant values
    15.
    发明公开
    Digital system with an output buffer with a switching current settable to load-independent constant values 审中-公开
    一种数字系统具有输出缓冲器电路具有可调节的常数和负载无关的输出电流

    公开(公告)号：EP1372265A1

    公开(公告)日：2003-12-17

    申请号：EP02425378.3

    申请日：2002-06-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Nicollini, Germano

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: H03K17/166 ,  H03K17/164

    Abstract: A digital system comprises a digital data processing unit (PROC), at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit (13) connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means (14, 15, IGEN1, IGEN2) for fixing the switching current to a value that is substantially constant and independent of the load and means (SN2-4, SP2-4) for selectively setting the value of the switching current and the processing unit (PROC) comprises means (REG) for storing a predetermined parameter; said means (REG) are connected to the selective setting means (SN2-4, SP2-4) for setting the values of the switching current as functions of the predetermined parameter.

    Abstract translation: 一种数字系统，包括一个数字数据处理单元（PROC），连接到所述处理单元响应于来自所述处理单元和至少一个用户单元（13）到达的数字信号，以产生输出信号的至少一个输出缓冲器连接作为输出缓冲 负载。 与以确保没有输出缓冲区的切换电流的图可以被设置为不同的值，输出缓冲器包括装置（14，15，IGEN1，IGEN2），用于切换电流固定为一个值那样基本上是恒定的和独立的 负载和用于有选择地设定切换电流和所述处理单元（PROC）的值的装置（SN2-4，SP2-4）包括用于存储预定参数的装置（REG）; 所述装置（REG）被连接到所述选择性设定装置（SN2-4，SP2-4）用于设定切换电流的值作为预定参数的功能。

    A receiver portion of a telephone
    17.
    发明公开
    A receiver portion of a telephone 有权
    Empfängerteileines电话

    公开(公告)号：EP1071206A1

    公开(公告)日：2001-01-24

    申请号：EP99830462.0

    申请日：1999-07-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pernici, Sergio ,  Nicollini, Germano

    IPC: H03G3/34

    CPC classification number: H03G3/348

    Abstract: The receiver portion comprises a differential amplifier stage (12) with a single output, an electroacoustic transducer (13) connected between the output, via a capacitor (Cest), and ground and a unit (20) for controlling switching on/off, connected to the differential stage (12) for the activation or deactivation thereof.
    To prevent annoying noises in the transducer upon switching on and off, the differential stage comprises an operational amplifier (16) having a first capacitor (C1) and a second capacitor (C2) in series with the inverting and the non-inverting input terminals, a third capacitor (C3) connected between the inverting input and the output of the operational amplifier (16), a fourth capacitor (C4) connected between the non-inverting input and a first reference-voltage terminal (ground), a first switching capacitor (C1S) connectible alternatively between a second and a third reference-voltage terminal (RF2, RF3) or between the first input and the output of the operational amplifier (16), a second switching capacitor (C2S) connectible alternatively between a fourth and a fifth reference-voltage terminal (RF4, RF5) or between the second input of the operational amplifier (16) and the fifth reference-voltage terminal (RFS). A switching unit (15) comprises switching means (15a, 15b) controlled by the unit (20) for controlling switching on/off in order to interrupt the connection between the input terminals of the differential stage (12) and the outputs of the previous stage (11) and to connect the differential input terminals (INP1, INP2) to one another for a predetermined period of time (Δt) which starts from the activation of the differential stage (12).

    Abstract translation: 接收器部分包括具有单个输出的差分放大器级（12），经由电容器（Cest）连接在输出端之间的电声换能器（13）和用于控制开/关的单元（20），连接 到达差动级（12）以激活或去激活。 为了防止在接通和断开时在换能器中产生麻烦的噪声，差动级包括具有与反相和非反相输入端串联的第一电容器（C1）和第二电容器（C2）的运算放大器（16） 连接在运算放大器（16）的反相输入和输出端之间的第三电容器（C3），连接在非反相输入端和第一基准电压端子（地）之间的第四电容器（C4），第一开关电容器 （C1S），可替换地可连接在第二和第三参考电压端子（RF2，RF3）之间或在运算放大器（16）的第一输入和输出之间，第二开关电容器（C2S）可替代地在第四和第 第五参考电压端子（RF4，RF5）或运算放大器（16）的第二输入端与第五参考电压端子（RFS）之间。 开关单元（15）包括由单元（20）控制的用于控制开/关的开关装置（15a，15b），以便中断差分级（12）的输入端与前一个 阶段（11），并且将差分输入端子（INP1，INP2）彼此连接预定时间段（DELTA t），其从差动级（12）的启动开始。

    Receiving section of a telephone
    18.
    发明公开
    Receiving section of a telephone 审中-公开
    电话接收部分

    公开(公告)号：EP1052832A1

    公开(公告)日：2000-11-15

    申请号：EP99830297.0

    申请日：1999-05-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicollini, Germano ,  Pernici, Sergio

    IPC: H04M1/60 ,  H03G3/34

    CPC classification number: H04M1/6016 ,  H03G3/348

    Abstract: A processing unit (11) with balanced outputs transfers a received digital signal (RX-IN) to an amplification unit (12) with balanced inputs and outputs. A control unit (20) enables or disables the processing (11) and amplification (12) units in response to a power up/power down signal (PD). To prevent disturbances due to power up/power down transients from appearing in the acoustic transducer (13) connected between the outputs of the amplification unit (12), switches (M1A, M1B) are provided between the outputs of the processing unit (11) and the inputs of the amplification unit (12), and delay means (21-24) are provided to produce, according to a predetermined program, enabling/disabling control signals for the processing (11) and amplification (12) units and control signals for the switches (M1A, M1B).

    Abstract translation: 具有平衡输出的处理单元（11）将接收到的数字信号（RX-IN）传送到具有平衡输入和输出的放大单元（12）。 控制单元（20）响应于加电/断电信号（PD）启用或禁用处理（11）和放大（12）单元。 为了防止由于在连接在放大单元（12）的输出端之间的声学​​换能器（13）中出现由上电/断电瞬变引起的干扰，在处理单元（11）的输出之间提供开关（M1A，M1B） 并且提供放大单元（12）和延迟装置（21-24）的输入以根据预定程序产生用于处理（11）和放大（12）单元的控制信号和控制信号 对于开关（M1A，M1B）。

    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
    20.
    发明公开
    High-precision calibration circuit calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 有权
    用于校准集成电路的可调电容的时间常数依赖于电容高精度校准电路

    公开(公告)号：EP1962420A1

    公开(公告)日：2008-08-27

    申请号：EP07425099.4

    申请日：2007-02-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Nicollini, Germano

    IPC: H03H1/02 ,  H03H7/01

    CPC classification number: H03H7/0153 ,  H03H1/02 ,  H03H2210/021 ,  H03H2210/043

    Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising:
    - a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors;
    - an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels;
    - a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step,

    characterized in that
    in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

    Abstract translation: 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容（C（VAR（REG_BUS））和包括校准环路（U_CV，CMP，TG_SAR），适合在几个连续的步骤来进行校准周期（C_LOOP）（ST_1，...，圣4 ），包括： - 一个可控电容单元（U_CV）适合于在校准步骤的开始接收的控制信号（SAR_BUS），并在开关电容器阵列（C_AR1）包括也可以由控制信号被选择性地激活以连接 到第一公共节点（N_u），其具有，在一个积分区间（P2）结束时，一个电压值（VRC）根据激活的电容器的总电容值; - 评估单元（CMP）适合于比较该电压 值（VRC）与参考 ENCE电压以输出逻辑信号（OUT_CMP），基于该比较结果可以进行第一和第二逻辑电平之间的转变; - 控制和定时单元（TG_SAR）适合于接收所述逻辑信号（OUT_CMP）和改变控制信号（SAR_BUS）基于其，以便进行随后的校准步骤中，在“那个”中设置的所述校准步骤为特征的， 在逻辑信号（OUT_CMP）的所述积分间隔（P2）在预设持续时间的比较区间（P3），它允许一个过渡（TL，T4）的端部之前，所述连续校准步骤的开始时发生。

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