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    Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter
    3.
    发明公开
    Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter 有权
    一种用于在最后Integrateurs的输出的Σ-Δ转换器和相关联的换能器增加的抖动信号的方法

    公开(公告)号：EP1727287A1

    公开(公告)日：2006-11-29

    申请号：EP05425374.5

    申请日：2005-05-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pinna, Carlo ,  Pernici, Sergio ,  Nagari, Angelo

    IPC: H03M3/02 ,  H03M3/04

    CPC classification number: H03M3/332 ,  H03M3/424 ,  H03M3/454

    Abstract: A single-ended or differential single-stage or multi-stage sigma-delta analog-to-digital converter comprises at least a switched-capacitor integrator having a switched-capacitor structure, to an input of which a signal to be sampled is applied, and an amplifier in cascade thereto, and has circuit means coupled to the amplifier for feeding an analog dither signal to a virtual ground node of the amplifier.

    Abstract translation: 单端或差分单级或多级Σ-Δ模拟到数字转换器包括具有至少一个开关电容器积分器的开关电容器结构，在其中的输入信号被采样被施加 并在级联放大器于此，并且电路装置，耦合到所述放大器用于馈送到模拟抖动信号到所述放大器的虚拟接地节点。

    Single-loop switched-capacitors analog-to-digital sigma-delta converter
    5.
    发明公开
    Single-loop switched-capacitors analog-to-digital sigma-delta converter 有权
    Einschleifiger Sigma-Delta Analog / Digital-Wandler mit geschalteten Kondensatoren

    公开(公告)号：EP1732229A1

    公开(公告)日：2006-12-13

    申请号：EP05425416.4

    申请日：2005-06-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pernici, Sergio ,  Garibaldi, Federico

    IPC: H03M3/04

    CPC classification number: H03M3/454 ,  H03M3/424

    Abstract: A single-loop differential switched-capacitors Sigma-Delta converter has a three stage double-sampling architecture, a reduced current consumption and is stable even for large input dynamics. The latter characteristic makes it suitable for RF applications.
    The novel three-stage multi-bit double-sampled architecture of a Sigma-Delta converter has a single-loop architecture, that is all integrators are included in a same feedback loop. This has been made possible by an effective choice of the type of integrators of the converter connected in cascade.
    Thanks to its innovative architecture, the functioning of the converter is less sensitive to non idealities of the operational amplifiers of the integrators.

    Abstract translation: 单回路差分开关电容器Σ-Δ转换器具有三级双采样架构，降低了电流消耗，并且即使对于大输入动态也是稳定的。 后者的特点使其适用于射频应用。 Sigma-Delta转换器的新型三级多位双采样架构具有单回路架构，即所有积分器都包含在相同的反馈环路中。 这是通过有效选择级联连接器的积分器的类型来实现的。 由于其创新的架构，转换器的功能对集成商的运算放大器的非理想性较不敏感。

    A receiver portion of a telephone
    7.
    发明公开
    A receiver portion of a telephone 有权
    Empfängerteileines电话

    公开(公告)号：EP1071206A1

    公开(公告)日：2001-01-24

    申请号：EP99830462.0

    申请日：1999-07-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pernici, Sergio ,  Nicollini, Germano

    IPC: H03G3/34

    CPC classification number: H03G3/348

    Abstract: The receiver portion comprises a differential amplifier stage (12) with a single output, an electroacoustic transducer (13) connected between the output, via a capacitor (Cest), and ground and a unit (20) for controlling switching on/off, connected to the differential stage (12) for the activation or deactivation thereof.
    To prevent annoying noises in the transducer upon switching on and off, the differential stage comprises an operational amplifier (16) having a first capacitor (C1) and a second capacitor (C2) in series with the inverting and the non-inverting input terminals, a third capacitor (C3) connected between the inverting input and the output of the operational amplifier (16), a fourth capacitor (C4) connected between the non-inverting input and a first reference-voltage terminal (ground), a first switching capacitor (C1S) connectible alternatively between a second and a third reference-voltage terminal (RF2, RF3) or between the first input and the output of the operational amplifier (16), a second switching capacitor (C2S) connectible alternatively between a fourth and a fifth reference-voltage terminal (RF4, RF5) or between the second input of the operational amplifier (16) and the fifth reference-voltage terminal (RFS). A switching unit (15) comprises switching means (15a, 15b) controlled by the unit (20) for controlling switching on/off in order to interrupt the connection between the input terminals of the differential stage (12) and the outputs of the previous stage (11) and to connect the differential input terminals (INP1, INP2) to one another for a predetermined period of time (Δt) which starts from the activation of the differential stage (12).

    Abstract translation: 接收器部分包括具有单个输出的差分放大器级（12），经由电容器（Cest）连接在输出端之间的电声换能器（13）和用于控制开/关的单元（20），连接 到达差动级（12）以激活或去激活。 为了防止在接通和断开时在换能器中产生麻烦的噪声，差动级包括具有与反相和非反相输入端串联的第一电容器（C1）和第二电容器（C2）的运算放大器（16） 连接在运算放大器（16）的反相输入和输出端之间的第三电容器（C3），连接在非反相输入端和第一基准电压端子（地）之间的第四电容器（C4），第一开关电容器 （C1S），可替换地可连接在第二和第三参考电压端子（RF2，RF3）之间或在运算放大器（16）的第一输入和输出之间，第二开关电容器（C2S）可替代地在第四和第 第五参考电压端子（RF4，RF5）或运算放大器（16）的第二输入端与第五参考电压端子（RFS）之间。 开关单元（15）包括由单元（20）控制的用于控制开/关的开关装置（15a，15b），以便中断差分级（12）的输入端与前一个 阶段（11），并且将差分输入端子（INP1，INP2）彼此连接预定时间段（DELTA t），其从差动级（12）的启动开始。

    Receiving section of a telephone
    8.
    发明公开
    Receiving section of a telephone 审中-公开
    电话接收部分

    公开(公告)号：EP1052832A1

    公开(公告)日：2000-11-15

    申请号：EP99830297.0

    申请日：1999-05-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Nicollini, Germano ,  Pernici, Sergio

    IPC: H04M1/60 ,  H03G3/34

    CPC classification number: H04M1/6016 ,  H03G3/348

    Abstract: A processing unit (11) with balanced outputs transfers a received digital signal (RX-IN) to an amplification unit (12) with balanced inputs and outputs. A control unit (20) enables or disables the processing (11) and amplification (12) units in response to a power up/power down signal (PD). To prevent disturbances due to power up/power down transients from appearing in the acoustic transducer (13) connected between the outputs of the amplification unit (12), switches (M1A, M1B) are provided between the outputs of the processing unit (11) and the inputs of the amplification unit (12), and delay means (21-24) are provided to produce, according to a predetermined program, enabling/disabling control signals for the processing (11) and amplification (12) units and control signals for the switches (M1A, M1B).

    Abstract translation: 具有平衡输出的处理单元（11）将接收到的数字信号（RX-IN）传送到具有平衡输入和输出的放大单元（12）。 控制单元（20）响应于加电/断电信号（PD）启用或禁用处理（11）和放大（12）单元。 为了防止由于在连接在放大单元（12）的输出端之间的声学​​换能器（13）中出现由上电/断电瞬变引起的干扰，在处理单元（11）的输出之间提供开关（M1A，M1B） 并且提供放大单元（12）和延迟装置（21-24）的输入以根据预定程序产生用于处理（11）和放大（12）单元的控制信号和控制信号 对于开关（M1A，M1B）。

    Integrated circuit with device for protecting against electrostatic discharges
    9.
    发明公开
    Integrated circuit with device for protecting against electrostatic discharges 审中-公开
    集成电路具有用于防止静电放电保护装置

    公开(公告)号：EP2023392A1

    公开(公告)日：2009-02-11

    申请号：EP07425517.5

    申请日：2007-08-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Pernici, Sergio

    IPC: H01L27/02

    CPC classification number: H01L27/0288

    Abstract: Integrated circuit (20) comprising:
    - a substrate of semiconductive material;
    - a first circuit environment (CE_1) made from said substrate, comprising a first pair of power supply terminals (VDD1,GND1) to receive a first power supply voltage applicable between said terminals (VDD1,GND1) and also comprising an output terminal (ou1);
    - a second circuit environment (CE_2) made from said substrate, comprising a second pair of power supply terminals (VDD2,GND2), distinct from said first pair of terminals (VDD1,GND1), to receive a second power supply voltage applicable between terminals of said second pair and also comprising an input terminal (In2) electrically coupled with said output terminal (Ou1).
    The integrated circuit comprises a device for protecting from electrostatic discharges comprising an integrated resistive device (Rcd) connected between said output terminal (Ou1) and said input terminal (In2).

    Abstract translation: 集成电路（20），包括： - 半导体材料的基板; - 第一电路环境（CE_1）从所述基板制成的，包括：第一对供电端子（VDD1，GND1）中以接收适用所述端子（VDD1，GND1），因此，其包括输出端之间的第一电源电压（OU1 ）; - 第二电路环境（CE_2）从所述基板制成，包括第二对电源端子（VDD 2，GND2），从所述第一对端子（VDD1，GND1）中，不同的接收适用端子之间的第二电源电压 所述第二对等包括电耦合到所述输出端子（OU1）输入端（IN2）的。 该集成电路包括一个装置用于从静电放电包括集成电阻性装置（RCD），其连接所述输出端子（OU1）之间的保护和所述输入端（IN2）。

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