公开(公告)号：EP1962420A1

公开(公告)日：2008-08-27

申请号：EP07425099.4

申请日：2007-02-23

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Nicollini, Germano

IPC: H03H1/02 ,  H03H7/01

CPC classification number: H03H7/0153 ,  H03H1/02 ,  H03H2210/021 ,  H03H2210/043

Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising:
- a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors;
- an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels;
- a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step,

characterized in that
in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

Abstract translation: 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容（C（VAR（REG_BUS））和包括校准环路（U_CV，CMP，TG_SAR），适合在几个连续的步骤来进行校准周期（C_LOOP）（ST_1，...，圣4 ），包括： - 一个可控电容单元（U_CV）适合于在校准步骤的开始接收的控制信号（SAR_BUS），并在开关电容器阵列（C_AR1）包括也可以由控制信号被选择性地激活以连接 到第一公共节点（N_u），其具有，在一个积分区间（P2）结束时，一个电压值（VRC）根据激活的电容器的总电容值; - 评估单元（CMP）适合于比较该电压 值（VRC）与参考 ENCE电压以输出逻辑信号（OUT_CMP），基于该比较结果可以进行第一和第二逻辑电平之间的转变; - 控制和定时单元（TG_SAR）适合于接收所述逻辑信号（OUT_CMP）和改变控制信号（SAR_BUS）基于其，以便进行随后的校准步骤中，在“那个”中设置的所述校准步骤为特征的， 在逻辑信号（OUT_CMP）的所述积分间隔（P2）在预设持续时间的比较区间（P3），它允许一个过渡（TL，T4）的端部之前，所述连续校准步骤的开始时发生。

公开(公告)号：EP2023392A1

公开(公告)日：2009-02-11

申请号：EP07425517.5

申请日：2007-08-08

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Pernici, Sergio

IPC: H01L27/02

CPC classification number: H01L27/0288

Abstract: Integrated circuit (20) comprising:
- a substrate of semiconductive material;
- a first circuit environment (CE_1) made from said substrate, comprising a first pair of power supply terminals (VDD1,GND1) to receive a first power supply voltage applicable between said terminals (VDD1,GND1) and also comprising an output terminal (ou1);
- a second circuit environment (CE_2) made from said substrate, comprising a second pair of power supply terminals (VDD2,GND2), distinct from said first pair of terminals (VDD1,GND1), to receive a second power supply voltage applicable between terminals of said second pair and also comprising an input terminal (In2) electrically coupled with said output terminal (Ou1).
The integrated circuit comprises a device for protecting from electrostatic discharges comprising an integrated resistive device (Rcd) connected between said output terminal (Ou1) and said input terminal (In2).

Abstract translation: 集成电路（20），包括： - 半导体材料的基板; - 第一电路环境（CE_1）从所述基板制成的，包括：第一对供电端子（VDD1，GND1）中以接收适用所述端子（VDD1，GND1），因此，其包括输出端之间的第一电源电压（OU1 ）; - 第二电路环境（CE_2）从所述基板制成，包括第二对电源端子（VDD 2，GND2），从所述第一对端子（VDD1，GND1）中，不同的接收适用端子之间的第二电源电压 所述第二对等包括电耦合到所述输出端子（OU1）输入端（IN2）的。 该集成电路包括一个装置用于从静电放电包括集成电阻性装置（RCD），其连接所述输出端子（OU1）之间的保护和所述输入端（IN2）。

公开(公告)号：EP1710917A1

公开(公告)日：2006-10-11

申请号：EP06116241.8

申请日：2003-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nicollini, Germano ,  Martignone, Riccardo

IPC: H03M1/68

CPC classification number: H03M1/687 ,  H03M1/68 ,  H03M1/745 ,  H03M1/765

Abstract: A digital to analog converter to convert into an analog quantity a digital code of L bits, comprising
- a first group of L current generators codified in binary form (MDON-MD2N),
- first selection means (SDON-SD2N) of the L current generators,
- means for conveying onto a common output node (N3) the current (IL) of the selected generators,
- control means (TRANSCOD-3BIT') to selectively operate the selection means (SD0N-SD2N) according to the digital code of L bits.
The converter further comprises a second group of L current generators (MD0P-MD2P) codified in binary form and second selection means (SD0P-SD2P) of the second group of L current generators.
The control means comprise a selection logic that alternatively habilitates the use of the first or the second group of generators according to whether the digital code to be converted does (D11=1) or does not (D11=0) exceed, respectively, a predetermined value.

Abstract translation: 一种数模转换器，用于将L位的数字码转换为模拟量，包括：以二进制形式编码的第一组L电流发生器（MDON-MD2N），L电流的第一选择装置（SDON-SD2N） 发电机， - 用于将所选发电机的电流（IL）传送到公共输出节点（N3）的装置， - 控制装置（TRANSCOD-3BIT'），以根据数字代码选择性地操作选择装置（SD0N-SD2N） L位。 转换器还包括以二进制形式编码的第二组L电流发生器（MD0P-MD2P）和第二组L电流发生器的第二选择装置（SD0P-SD2P）。 所述控制装置包括选择逻辑，所述选择逻辑根据所述要转换的数字码是否（D11 = 1）或不（D11 = 0）分别超过预定的 值。

公开(公告)号：EP1601113A1

公开(公告)日：2005-11-30

申请号：EP04425375.5

申请日：2004-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano ,  Confalonieri, Pierangelo ,  Martignone, Riccardo

IPC: H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a wide-band transmission system, particularly for employment in cellular telephony systems that adopt the WCDMA standard. The system comprises means for generating two digital signals containing information to be transmitted, means for converting into analog form the two signals comprising, for each signal to be converted, a digital-analog converter (DAC) followed by a low-pass filter (LOW-PASS), means for modulating both in phase and in quadrature a radio frequency carrier with the two signals issuing from the low-pass filters (LOW-PASS), and means for transmitting the modulated carrier in accordance with a predetermined emission mask. If the system is to be capable of being integrated into an area of small extent and is to have a low current consumption, the low-pass filter (LOW-PASS) is an active filter of the second order continuous in time and current-coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency by at least as much as is necessary to respect the predetermined emission mask.

Abstract translation: 描述了一种宽带传输系统，特别是在采用WCDMA标准的蜂窝电话系统中的就业。 该系统包括用于产生包含要发送的信息的两个数字信号的装置，用于将两个信号转换成模拟形式的装置，对于每个要转换的信号，包括数模转换器（DAC）和随后的低通滤波器（LOW -PASS），用于利用从低通滤波器（LOW-PASS）发出的两个信号同时和正交调制无线电频率载波的装置，以及用于根据预定的发射掩模传送调制载波的装置。 如果系统能够集成到小范围的区域并且具有低电流消耗，则低通滤波器（LOW-PASS）是时间上连续的二阶有源滤波器和电流耦合 数字模拟转换器（DAC）的输出端和数模转换器（DAC）是以大于奈奎斯特频率的采样频率工作的电流导向型转换器，其至少必须相当于必须的 预定的发射掩模。

公开(公告)号：EP2026467A1

公开(公告)日：2009-02-18

申请号：EP07425478.0

申请日：2007-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Martignone, Riccardo

IPC: H03M1/06

CPC classification number: H03M1/0648 ,  H03M1/687 ,  H03M1/747

Abstract: A current steering digital-analog converter (1) for converting a digital code (In-cod) into an analog signal (Vout) is described. The converter comprises:
- a substrate of semiconductor material;
- an array (2) of current generators (MD0, MD1, M1-M15) integrated in the substrate;
- a common summation node (NC1) and switching means (3) controllable on the basis of the digital code for connecting/disconnecting the current generators (MD0, MD1, M1-M15) to/from the common summation node (NC1).
The current generators (MD0, MD1, M1-M15) are such as to provide the common summation node (NC1) with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator (MD0) of the array (2) of generators (MD0, MD1, M1-M15).
The current generator (MD0) is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

Abstract translation: 描述用于将数字代码（In-cod）转换为模拟信号（Vout）的电流转向数模转换器（1）。 该转换器包括： - 半导体材料的衬底; - 集成在基板中的电流发生器（MD0，MD1，M1-M15）的阵列（2） - 根据用于将电流发生器（MD0，MD1，M1-M15）与公共求和节点（NC1）连接/断开的数字代码可控的公共求和节点（NC1）和切换装置（3）。 电流发生器（MD0，MD1，M1-M15）的目的是为了提供公共求和节点（NC1），该电流具有与通过电流提供给求和节点的单位电流值相比的两倍的功率的多个值 发生器（2）的发生器（MD0）（MD0，MD1，M1-M15）。 电流发生器（MD0）被分成至少等于2的彼此并联的基本数量的模块化电流产生元件。

公开(公告)号：EP1962421A1

公开(公告)日：2008-08-27

申请号：EP07425100.0

申请日：2007-02-23

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Zamprogno, Marco

IPC: H03H1/02 ,  H03H7/01

CPC classification number: H03H1/02 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/043

Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitor (C var (REG_BUS)) and including a calibration loop (RC_DEL, DFF, TG_SAR) comprising:
- a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
- a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
- a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),

characterized in that
said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.

Abstract translation: 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容器（C VAR（REG_BUS）），并且包括一个校准循环（RC_DEL，DFF，TG_SAR），包括： - 一个可控电容单元（RC_DEL）适合于接收控制信号（SAR_BUS）和包括至少一个 开关电容器（C_AR1，CAR_2）的阵列也可以由控制信号（SAR_BUS），单元（RC_DEL）的方式来激活正被检查，以输出由参数为特征的第一信号（OUT_DEL）上的电容的量根据 由控制信号（SAR_BUS）激活阵列（C_AR1，CAR_2）的; - 一个比较单元（DFF），其适于接收所述第一信号（OUT_DEL）评估是否所述参数是否满足预设条件，并输出比较信号（OUT_DFF）代表评估结果的一个; - 控制和定时逻辑单元（TG_SAR）适合于基于所述比较信号（OUT_DFF）接收比较信号（OUT_DFF）来改变该控制信号（SAR_BUS）表示，在这特点第一信号（OUT_DEL）是一个逻辑信号，并且 所述参数是所述第一信号的时间参数。