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    Internal addressing structure of a semiconductor memory
    11.
    发明公开
    Internal addressing structure of a semiconductor memory 有权
    Interne Addressierungsstruktur eines Halbleiterspeichers

    公开(公告)号：EP1195770A1

    公开(公告)日：2002-04-10

    申请号：EP00830655.7

    申请日：2000-10-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi

    IPC: G11C8/04

    CPC classification number: G11C8/04

    Abstract: Internal addressing structure for a semiconductor memory with at least two memory banks, comprising a counter (61,62) associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, first circuit means (75,76) for causing a selective updating of the counters, second circuit means (71,72,IN_A) for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus (ADD), corresponding to an initial memory location, and third circuit means (77,71,72) capable of detecting a first signal (ALE), supplied to the memory from the outside and indicating the presence of a digital code on the said bus, to cause the said common initial digital code to be loaded into the counters. The said first circuit means are capable of identifying, on the basis of the said initial address, the bank to which the initial memory location belongs, and of consequently causing the periodic updating of the counters in a sequence which depends on the bank to which the initial memory location belongs, in such a way that successive memory locations preceding or following the said initial location are addressed in sequence, each of these successive locations belonging to a corresponding memory bank, according to an interlaced system.

    Abstract translation: 具有至少两个存储体的半导体存储器的内部寻址结构，包括与每个存储器组相关联的计数器（61,62），能够产生用于寻址相应存储单元中的位置的数字代码序列，第一电路装置（75 ，76），用于选择性地更新计数器，第二电路装置（71,72，IN_A），用于将共同的初始数字代码加载到计数器中，形成通过寻址行从外部提供给存储器的初始地址的一部分 对应于初始存储器位置的总线（ADD）和能够检测第一信号（ALE）的第三电路装置（77,71,72），从外部提供给存储器并指示数字代码的存在 所述总线，使所述常见的初始数字代码被加载到计数器中。 所述第一电路装置能够基于所述初始地址识别初始存储器位置所属的存储体，并且因此导致按顺序定期更新计数器，该序列取决于存储器 初始存储器位置属于这样一种方式，使得在所述初始位置之前或之后的连续存储器位置被顺序地寻址，这些连续位置中的每一个属于对应的存储体，根据隔行扫描系统。

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