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    Voltage level shifter device, particularly for a non-volatile memory
    3.
    发明公开
    Voltage level shifter device, particularly for a non-volatile memory 失效
    Spannungspegelumsetzungsverfahren，insbesonderefürnichtflüchtigenSpeicher

    公开(公告)号：EP0862183A1

    公开(公告)日：1998-09-02

    申请号：EP97830085.3

    申请日：1997-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fontana, Marco ,  Barcella, Antonio

    IPC: G11C16/06 ,  G11C8/00

    CPC classification number: G11C16/12 ,  G11C8/08

    Abstract: In a first operation mode the level shifter (36) transmits as output a logic input signal (S i ) and in a second operation mode it shifts the high logic level of the input signal from a low (V dd ) to a high voltage (V pp ). The level shifter comprises a CMOS switch (42) and a pull-up transistor (43); the CMOS switch (42) comprises an NMOS transistor (45) and a PMOS transistor (44) which are connected in parallel between the input (37) and the output (39) of the shifter and have respective control terminals connected to a first supply line (4) at low voltage (V dd ) and, respectively, to a control line (46) connected to ground in the first operation mode and to the high voltage (V pp ) in the second operation mode; the pull-up transistor (43) is connected between the output (39) of the shifter and a second supply line (2) switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line (4).

    Abstract translation: 在第一操作模式中，电平移位器（36）作为输出发送逻辑输入信号（Si），并且在第二操作模式中，将输入信号的高逻辑电平从低（Vdd）移位到高电压（Vpp） 。 电平移位器包括CMOS开关（42）和上拉晶体管（43）; CMOS开关（42）包括在移位器的输入（37）和输出（39）之间并联连接的NMOS晶体管（45）和PMOS晶体管（44），并且各自的控制端子连接到第一电源 线路（4）在低电压（Vdd）下分别连接到在第一操作模式中连接到地的控制线（46）和第二操作模式中的高电压（Vpp）; 所述上拉晶体管43连接在所述移位器的输出端和所述低电压和高电压之间的第二供电线路之间，并具有与所述第一供电线路连接的控制端子， 。

    Method for reading a memory, particularly a non-volatile memory
    9.
    发明公开
    Method for reading a memory, particularly a non-volatile memory 有权
    Verfahren zum Lesen eines Speichers，insbesondere einesnichtflüchtigenSpeichers

    公开(公告)号：EP1017059A1

    公开(公告)日：2000-07-05

    申请号：EP98830801.1

    申请日：1998-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Fontana, Marco

    IPC: G11C7/00

    CPC classification number: G11C7/1018

    Abstract: A method for reading a memory, particularly a non-volatile memory, whose particularity is that it comprises the steps of:

    generating a memory enable signal (CE);
    generating a signal (ALE) for the visibility, inside the memory, of address signals generated externally with respect to the memory, the address signals being adapted to allow access to corresponding memory locations of the memory;
    generating a signal (RD) for the synchronous advancement of the read operation within the memory;
    each change of state of the memory enable signal (CE), together with a change of state of the address signals, being matched by different cycles for reading the memory, the different read cycles being enabled according to the state of the signal (ALE) for the visibility, inside the memory, of address signals generated externally to the memory, the logic state of the visibility signal switching between the high logic state, the low logic state and the pulsed state; emission of the data read from the memory being correlated to the state transition of the signal (RD) for the synchronous advancement of the reading of the memory.

    Abstract translation: 一种用于读取存储器，特别是非易失性存储器的方法，其特征在于其包括以下步骤：产生存储器使能信号（CE）; 产生用于在存储器内的对于存储器在外部产生的地址信号的可见性的信号（ALE），所述地址信号适于允许访问存储器的相应存储器位置; 产生用于在存储器内同步提前读取操作的信号（RD）; 存储器使能信号（CE）的状态的每个改变与地址信号的状态的改变一起被用于读取存储器的不同周期匹配，根据信号（ALE）的状态启用不同的读取周期， 为了存储器内部可见的内部存储器中产生的地址信号的可见性，可视信号的逻辑状态在高逻辑状态，低逻辑状态和脉冲状态之间切换; 从存储器读取的数据的发射与用于对存储器的读取的同步提前的信号（RD）的状态转换相关。

    Voltage regulator with voltage drop compensation for a programming circuitry of non-volatile electrically programmable memory cells
    10.
    发明公开
    Voltage regulator with voltage drop compensation for a programming circuitry of non-volatile electrically programmable memory cells 失效
    电压调节器具有用于非易失性的编程和电可编程存储单元的电压降的补偿电路

    公开(公告)号：EP0905710A1

    公开(公告)日：1999-03-31

    申请号：EP97830484.8

    申请日：1997-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fontana, Marco ,  Montanaro, Massimo

    IPC: G11C16/06 ,  G11C5/14 ,  G05F3/26

    CPC classification number: G11C16/30 ,  G05F3/262 ,  G11C5/147

    Abstract: The invention relates to a compensated voltage regulator (1) useful with programming circuitry for electrically programmable non-volatile memory cells in a cell matrix (3) which is divided in sectors (7), the regulator being of a type which includes a comparator (2) connected between first (Vpp) and second (GND) supply voltage references, and having:

    a first input terminal (+) which is supplied by a reference voltage (Vref);
    an output terminal (U) connected to the control terminal of an output MOS transistor (Mcasc) having a conduction terminal through which an output current (Iout) is passed and being connected to the memory cells by a program line (10);
    a second input terminal (-), feedback connected to said program line (10).

    A compensation block (20) is provided which is powered from said first voltage reference (Vpp) and has an input connected to both said output terminal (U) and said output transistor (Mcasc), and has an output connected to said output terminal (U) to duplicate a current (Iout*α) which is suitably attenuated with respect to the output current (Iout) and useful to modify the output voltage (Vg) of the comparator (2) included in the regulator.

    Abstract translation: 本发明涉及一个补偿电压调节器（1），用于在一个单元矩阵电可编程的非易失性存储器单元以编程电路有用（3）所有被划分成扇区（7），一个类型，其包括比较器的所述调节器（ 2）连接的第一（VPP）和第二（GND）供应电压基准，并具有之间：第一输入端（+），它是由一个基准电压（Vref）提供; 在输出端（U）连接到输出MOS晶体管具有通过输出电流的哪个（LOUT）被传递并且被连接到由程序线（10）的存储器单元的导通端子（Mcasc）的控制端子; 第二输入端子（ - ），反馈连接到所述编程线（10）。 这是从所述第一电压基准（Vpp）为动力的，并且具有连接到两个所述输出端子（U）和所述输出晶体管（Mcasc）输入，并具有连接到所述输出端子输出（A补偿块（20）提供的所有 U）复制一个电流（Iout *阿尔法）所有其适当相对于所述输出电流衰减（I OUT）和有用的修改比较器包括在所述调节器（2）的输出电压（Vg）。

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