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    Unbalanced latch and fuse circuit including the same
    1.
    发明授权
    Unbalanced latch and fuse circuit including the same 失效
    不平衡锁存电路和含有它们Schmelgsicherungsschatung

    公开(公告)号：EP0756379B1

    公开(公告)日：2003-09-24

    申请号：EP95830337.2

    申请日：1995-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Barcella, Antonio ,  Fontana, Marco

    IPC: H03K3/356 ,  G11C16/06

    CPC classification number: G11C7/20 ,  H03K3/356008 ,  H03K3/356104

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    Multiemitter bipolar transistor for bandgap reference circuits
    4.
    发明公开
    Multiemitter bipolar transistor for bandgap reference circuits 审中-公开
    Vielfachemitter-BipolartransistorfürBandabstands-Referenzschaltungen

    公开(公告)号：EP1220321A1

    公开(公告)日：2002-07-03

    申请号：EP00830851.2

    申请日：2000-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vendrame, Loris ,  Caprara, Paolo ,  Oddone, Giorgio ,  Barcella, Antonio

    IPC: H01L29/732 ,  H01L29/08

    CPC classification number: H01L29/7322 ,  H01L29/0813

    Abstract: The present invention relates a transistor comprising a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of said first type (P+) of conductivity inside said substrate region (14) and adjacent to a first terminal (C) of said transistor, a well (11) of second type (N) of conductivity placed inside said substrate region (14), characterized in that said well (11) of second type (N) of conductivity comprises at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of said transistor, and a plurality of third contact regions (10) of said first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, ..., E3) of said transistor interposed each one (10) other (12) by proper insulating shapes (20).

    Abstract translation: 本发明涉及一种晶体管，其包括在具有相同类型（P）导电性的半导体材料层中的第一类型（P）的基底区域（14），至少第一类型的第一接触区域（13） （14）内并与所述晶体管的第一端（C）相邻的电导率（P +），放置在所述衬底区域（14）内的第二类型（N）导电性阱（11），其特征在于： 所述第二类型（N）的导体的阱（11）包括与所述晶体管的第二端子（B）的区域相邻的至少第二接触区域（N）的第二接触区域（12），并且多个 与所述晶体管的第三端子（E1，...，E3）的多个区域相邻的所述第一类型导电性（P +）的第三接触区域（10）通过适当地插入每个（10）另一个（12） 绝缘形状（20）。

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    5.
    发明公开
    "Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method" 有权
    读取非易失性存储器与所读取的采样流中的可变电压，和装置操作用于该方法Verwirkligung

    公开(公告)号：EP1063654A1

    公开(公告)日：2000-12-27

    申请号：EP99830382.0

    申请日：1999-06-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Barcella, Antonio ,  Rolandi, Paolo

    IPC: G11C16/28

    CPC classification number: G11C16/28

    Abstract: A reading method for non-volatile memory cells is illustrated which comprises a first step in which a memory cell (P2) of the matrix is selected by the row decoder (5) and by the column multiplexer (4), a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell (P2) reaches a defined value and is characterized by a third step during which the selected cell (P2) is read with a sensing ratio depending on the reading voltage of said cell.
    Moreover a device for the reading of said cells is described, which comprises a modulation branch (MOD) with at least one selection transistor (MV10) and a load generator (23) associated to said modulation transistor (MV10) in such a way to modulate analogicly the transconductance of one of the two load transistors (M1, M2) in function of the reading voltage of the memory cell (P2).

    Abstract translation: 用于非易失性存储单元的读出方法被示出，其包括在其中基质的存储单元（P2）由行解码器选择的第一步骤（5）和由所述列多路复用器（4），预紧的第二步骤 和均衡哪个期间对所选存储器单元（P2）的漏极电极的电压达到规定值，并且是由所选择的小区（P2）在第三步骤期间为特征的读出与在所述的读出电压的感测比例根据 细胞。 更在用于所述单元的读取中描述了一种设备，其与在寻求一种方法来调节相关联的所述调制晶体管（MV10）至少一个选择晶体管（MV10）和负载生成器（23）包括一个调制分支（MOD） 在存储单元（P2）的读出电压的函数的两个负载晶体管（M1，M2）中的一个的analogicly跨导。

    Voltage level shifter device, particularly for a non-volatile memory
    8.
    发明公开
    Voltage level shifter device, particularly for a non-volatile memory 失效
    Spannungspegelumsetzungsverfahren，insbesonderefürnichtflüchtigenSpeicher

    公开(公告)号：EP0862183A1

    公开(公告)日：1998-09-02

    申请号：EP97830085.3

    申请日：1997-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fontana, Marco ,  Barcella, Antonio

    IPC: G11C16/06 ,  G11C8/00

    CPC classification number: G11C16/12 ,  G11C8/08

    Abstract: In a first operation mode the level shifter (36) transmits as output a logic input signal (S i ) and in a second operation mode it shifts the high logic level of the input signal from a low (V dd ) to a high voltage (V pp ). The level shifter comprises a CMOS switch (42) and a pull-up transistor (43); the CMOS switch (42) comprises an NMOS transistor (45) and a PMOS transistor (44) which are connected in parallel between the input (37) and the output (39) of the shifter and have respective control terminals connected to a first supply line (4) at low voltage (V dd ) and, respectively, to a control line (46) connected to ground in the first operation mode and to the high voltage (V pp ) in the second operation mode; the pull-up transistor (43) is connected between the output (39) of the shifter and a second supply line (2) switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line (4).

    Abstract translation: 在第一操作模式中，电平移位器（36）作为输出发送逻辑输入信号（Si），并且在第二操作模式中，将输入信号的高逻辑电平从低（Vdd）移位到高电压（Vpp） 。 电平移位器包括CMOS开关（42）和上拉晶体管（43）; CMOS开关（42）包括在移位器的输入（37）和输出（39）之间并联连接的NMOS晶体管（45）和PMOS晶体管（44），并且各自的控制端子连接到第一电源 线路（4）在低电压（Vdd）下分别连接到在第一操作模式中连接到地的控制线（46）和第二操作模式中的高电压（Vpp）; 所述上拉晶体管43连接在所述移位器的输出端和所述低电压和高电压之间的第二供电线路之间，并具有与所述第一供电线路连接的控制端子， 。

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