公开(公告)号：EP2599107B1

公开(公告)日：2016-12-21

申请号：EP11810872.9

申请日：2011-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  MURABITO, Domenico ,  FIORE, Letterio ,  MORALE, Giuseppe ,  ARENA, Giuseppe

IPC: H01L21/20 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3247 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A process for manufacturing a semiconductor device envisages the steps of: providing a semiconductor material body having at least one deep trench that extends through said body of semiconductor material starting from a top surface thereof; and filling the deep trench via an epitaxial growth of semiconductor material, thereby forming a columnar structure within the body of semiconductor material. The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench; in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth.

公开(公告)号：EP2599107A2

公开(公告)日：2013-06-05

申请号：EP11810872.9

申请日：2011-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  MURABITO, Domenico ,  FIORE, Letterio ,  MORALE, Giuseppe ,  ARENA, Giuseppe

IPC: H01L21/20 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3247 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A process for manufacturing a semiconductor device envisages the steps of: providing a semiconductor material body having at least one deep trench that extends through said body of semiconductor material starting from a top surface thereof; and filling the deep trench via an epitaxial growth of semiconductor material, thereby forming a columnar structure within the body of semiconductor material. The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench; in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth.

公开(公告)号：EP1911075A1

公开(公告)日：2008-04-16

申请号：EP06776161.9

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: - forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (Á 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100), - forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (¦ 1P ), - forming second sub-regions (D1,D1a) of the first type of conductivity by means of a second implant step with a second implant dose (¦ 1N ), - forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51), - carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

公开(公告)号：EP1908117A2

公开(公告)日：2008-04-09

申请号：EP06762482.5

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe ,  MAGRI', Angelo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7835

Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1,1a;10,11) with wide band gap comprising the steps of: - forming a screening structure (3a,20) on said semiconductor substrate (1,1a;10,11) comprising at least a dielectric layer (2,20) which leaves a plurality of areas of said semiconductor substrate (1,1a;10,11) exposed, - carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a first implanted region (4,40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a second implanted region (6,6c;60,61) inside said at least a first implanted region (4,40), - carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4,40;6,60).

Abstract translation: 用于在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法，包括以下步骤：在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20），其包括 至少使所述半导体衬底（1,1a，10,11）的多个区域露出的电介质层（2,20），在所述半导体衬底（1，1a，10,11）中至少进行第一类型掺杂物的离子注入 ，1a; 10,11）以形成至少第一注入区（4,40），在所述半导体衬底（1,1a; 10,11）中执行至少第二类型掺杂物的离子注入以形成在 在所述至少第一注入区域（4,40）内部的至少第二注入区域（6,6c; 60,61），以低热预算执行适合完成的第一类型和第二类型掺杂物的激活热处理 所述至少第一和第二注入区域（4,40; 6,60）的所述形成。

公开(公告)号：EP1908101A1

公开(公告)日：2008-04-09

申请号：EP06762481.7

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (Á 1 ) value on the semiconductor substrate (100), forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (Á 2 ) value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (¦ 1 ) , forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (Á 6 ) value, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).

公开(公告)号：EP1851804A2

公开(公告)日：2007-11-07

申请号：EP06723076.3

申请日：2006-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/10 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

Abstract: Power semiconductor device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), and a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlying each other, the resistivity of each layer being different from that of the other layers, and wherein said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24).