公开(公告)号：WO2007006764A2

公开(公告)日：2007-01-18

申请号：PCT/EP2006/064035

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.r.l. ,  ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

Inventor： ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

公开(公告)号：WO2007006504A3

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006672

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe ,  MAGRI', Angelo

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe ,  MAGRI', Angelo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1, 1a; 10, 11) with wide band gap comprising the steps of: forming a screening structure (3a, 20) on said semiconductor substrate (1, 1a; 10, 11) comprising at least a dielectric layer (2, 20) which leaves a plurality of areas of said semiconductor substrate (1, 1a; 10, 11) exposed, carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a first implanted region (4, 40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1, 1a; 10, 11) to form at least a second implanted region (6, 6c; 60, 61) inside said at least a first implanted region (4, 40), carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4, 40; 6, 60).

公开(公告)号：EP3930007A1

公开(公告)日：2021-12-29

申请号：EP21180931.4

申请日：2021-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  MAGRI', Angelo ,  ZANETTI, Edoardo ,  GUARNERA, Alfio

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36

Abstract: Electronic device (100) comprising: a semiconductor body (102) of silicon carbide; a body region (105) at a first surface of the semiconductor body; a source region (108) in the body region (105); a drain region (104) at a second surface of the semiconductor body (102); a doped region (120) extending seamlessly at the entire first surface (102a) of the semiconductor body (102) and including one or more first sub-regions (121) having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：EP1908117A2

公开(公告)日：2008-04-09

申请号：EP06762482.5

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： FRISINA, Ferruccio ,  SAGGIO, Mario, Giuseppe ,  MAGRI', Angelo

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L21/047 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/6653 ,  H01L29/7835

Abstract: Method for manufacturing electronic devices on a semiconductor substrate (1,1a;10,11) with wide band gap comprising the steps of: - forming a screening structure (3a,20) on said semiconductor substrate (1,1a;10,11) comprising at least a dielectric layer (2,20) which leaves a plurality of areas of said semiconductor substrate (1,1a;10,11) exposed, - carrying out at least a ion implantation of a first type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a first implanted region (4,40), carrying out at least a ion implantation of a second type of dopant in said semiconductor substrate (1,1a;10,11) to form at least a second implanted region (6,6c;60,61) inside said at least a first implanted region (4,40), - carrying out an activation thermal process of the first type and second type of dopant with low thermal budget suitable to complete said formation of said at least first and second implanted regions (4,40;6,60).

Abstract translation: 用于在具有宽带隙的半导体衬底（1,1a; 10,11）上制造电子器件的方法，包括以下步骤：在所述半导体衬底（1,1a; 10,11）上形成屏蔽结构（3a，20），其包括 至少使所述半导体衬底（1,1a，10,11）的多个区域露出的电介质层（2,20），在所述半导体衬底（1，1a，10,11）中至少进行第一类型掺杂物的离子注入 ，1a; 10,11）以形成至少第一注入区（4,40），在所述半导体衬底（1,1a; 10,11）中执行至少第二类型掺杂物的离子注入以形成在 在所述至少第一注入区域（4,40）内部的至少第二注入区域（6,6c; 60,61），以低热预算执行适合完成的第一类型和第二类型掺杂物的激活热处理 所述至少第一和第二注入区域（4,40; 6,60）的所述形成。