公开(公告)号：WO2007006505A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006673

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity forming the drain epitaxial layer (20) on the semiconductor substrate (100) , forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step forming second sub-regions (Dl, DIa) of the first type of conductivity by means of a second implant step forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51) , carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

Abstract translation: 一种集成在形成有漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤：至少形成 在所述半导体衬底（100）上形成所述漏极外延层（20）的所述第一导电类型的第一半导体外延层（21），通过第一选择性形成第二导电类型的第一子区域（51） 植入步骤通过形成表面半导体层（23）的第二注入步骤形成第一类型导电性的第二子区域（D1，DIa），其中形成第二导电类型的主体区域（40）与 所述第一子区域（51）进行热扩散处理，使得所述第一子区域（51）形成与所述主体区域（40）电接触的单个电连续列区域（50）。

公开(公告)号：WO2007006503A1

公开(公告)日：2007-01-18

申请号：PCT/EP2006/006671

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a power electronic device (30) comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity forming at least a second semiconductor layer (22) of a second type of conductivity value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity forming, above said at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of semiconductor layer (22) free from the plurality of said at least second implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D).

Abstract translation: 一种用于制造功率电子器件（30）的方法，包括以下步骤：形成第一类型的导电性的第一半导体层（21），其形成至少第二类型的电导率值的第二半导体层（22），其在第一半导体 在所述至少第二半导体层（22）中形成所述第一类型的导电形成的第一多个注入区域（D1），在所述至少第二半导体层（22）之上，表面（21），表面 在所述表面半导体层（26）中形成所述第一导电类型的半导体层（26），所述半导体层（26）在所述第二导电类型的主体区域（40）中形成，所述主体区域（40）与半导体层 从所述多个所述至少第二注入区域（D1）中，进行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续的注入区域（D）。

公开(公告)号：EP3800660A1

公开(公告)日：2021-04-07

申请号：EP20198891.2

申请日：2020-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA, Simone ,  CHIBBARO, Claudio ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe ,  LIZIO, Francesco

IPC: H01L23/31

Abstract: An electronic power device (25) is provided with: a substrate (2) of silicon carbide (SiC), having a front surface (2a) and a rear surface (2b), which lie in a horizontal plane (xy) and are opposite to one another along a vertical axis (z), the substrate including an active area (A'), provided in which are a number of doped regions (4), and an edge area (A"), which is not active, distinct from and surrounding the active area (A'); a dielectric region (8a) arranged above the front surface (2a), at least at the edge area (A"); and a passivation layer (20) arranged above the front surface (2a) of the substrate (2), in contact with the dielectric region (8a) in the edge area (A"). The passivation layer (20) comprises at least one anchorage region (22) that extends throughout the thickness of the dielectric region (8a) at the edge area (A"), such as to define a mechanical anchorage for the passivation layer (20).

公开(公告)号：EP3712962A1

公开(公告)日：2020-09-23

申请号：EP20164124.8

申请日：2020-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA, Simone ,  SAGGIO, Mario Giuseppe

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L21/329 ,  H01L29/20

Abstract: A merged-PN-Schottky, MPS, diode (30), comprising: an N substrate (3); a N- drift layer (2); a P-doped region (19') in the drift layer (2); an ohmic contact (19") on the P-doped region (19'); a plurality of cells (33) within the P-doped region and being portions of the drift layer where the P-doped region (19') is absent; an anode metallization (8) on the ohmic contact (19") and on said cells (33), to form junction-barrier contacts and Schottky contacts respectively. The P-doped region (19') has a grid-shaped layout separating from one another each cell (33) and defining, together with the cells (33), an active area (14) of the MPS diode (30); each cell (33) has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact (19") extends at the doped region (19') with continuity along the grid-shaped layout.

公开(公告)号：EP1911075A1

公开(公告)日：2008-04-16

申请号：EP06776161.9

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: - forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (Á 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100), - forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (¦ 1P ), - forming second sub-regions (D1,D1a) of the first type of conductivity by means of a second implant step with a second implant dose (¦ 1N ), - forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51), - carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).

公开(公告)号：EP1908101A1

公开(公告)日：2008-04-09

申请号：EP06762481.7

申请日：2006-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (Á 1 ) value on the semiconductor substrate (100), forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (Á 2 ) value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (¦ 1 ) , forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (Á 6 ) value, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).