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    Synchronous switching circuit for data recovery
    11.
    发明公开
    Synchronous switching circuit for data recovery 审中-公开
    Synchroner Schalter zurDatenrückgewinnung

    公开(公告)号：EP1128594A1

    公开(公告)日：2001-08-29

    申请号：EP00830131.9

    申请日：2000-02-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Guinea, Jesus ,  Rutar, Massimiliano ,  Tomasini, Luciano

    IPC: H04L7/033 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07

    CPC classification number: H03L7/07 ,  H03L7/0814 ,  H04L7/0083 ,  H04L7/0337

    Abstract: A switching circuit for switching an output (CKS) to one of a plurality of N input clock signals (CK1-CKN) which are delayed relative to one another comprises circuit means (31-316, 7) responding to a control (CNT) in order to enable the transmission, on the output signal (CKS), of a new signal (CK(i-1); CKi) of the plurality of input signals which is advanced or delayed relative to a current signal (CKi; CK(i-1)) of the plurality of input signals which is currently transmitted on the output signal (CKS), the circuit means (31-316, 7) enabling the transmission of the new signal (CK(i-1); CKi) before disabling the transmission of the current signal (CKi; CK(i-1)) on the output signal (CKS) so as to prevent the production of false signals during the switching of the output signal from one of the clock signals to another.

    Abstract translation: 用于将输出（CKS）切换为相对于彼此延迟的多个N个输入时钟信号（CK1-CKN）中的一个的切换电路包括响应于控制（CNT）的电路装置（31-316,77） 使得能够在输出信号（CKS）上传输相对于当前信号（CKi; CK（i（i））提前或延迟的多个输入信号的新信号（CK（i-1）; CKi） -1）），可以在输出信号（CKS）上发送的多个输入信号中，能够在新的信号（CK（i-1）; CKi）之前发送的电路装置（31-316,7） 禁止在输出信号（CKS）上传输当前信号（CKi; CK（i-1）），以防止在将输出信号从一个时钟信号切换到另一个时产生假信号。

    An output buffer for digital signals
    12.
    发明公开
    An output buffer for digital signals 审中-公开
    Ausgangspufferfürdigitale Signale

    公开(公告)号：EP1091492A1

    公开(公告)日：2001-04-11

    申请号：EP99830634.4

    申请日：1999-10-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomasini, Luciano ,  Clerici, Giancarlo

    IPC: H03K19/003 ,  H03K17/16

    CPC classification number: H03K19/00361 ,  H03K17/166 ,  H03K19/00384

    Abstract: The buffer comprises means (20) for reducing the slope of the input signal (Vin) and a negative feedback circuit (22) which generates a regulating signal dependent on the variation of the output signal (Vout) and applies the regulating signal (If) to the input of the buffer.
    A precise regulation of the slope, independent of variations in the production process and of environmental conditions, is achieved.

    Abstract translation: 缓冲器包括用于减小输入信号（Vin）的斜率的装置（20）和负反馈电路（22），该负反馈电路根据输出信号（Vout）的变化产生调节信号，并施加调节信号（If） 到缓冲区的输入。 实现斜率的精确调节，与生产过程和环境条件的变化无关。

    Voltage follower circuit
    13.
    发明公开
    Voltage follower circuit 审中-公开
    Spannungsfolgerschaltung

    公开(公告)号：EP1041713A1

    公开(公告)日：2000-10-04

    申请号：EP99830180.8

    申请日：1999-03-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomasini, Luciano ,  Clerici, Giancarlo

    IPC: H03F3/30

    CPC classification number: H03F3/3071 ,  H03F3/3001

    Abstract: A first NPN transistor (Q 1 ) is connected in the emitter follower configuration with a first PNP transistor (Q 2 ) as the load element. A second NPN transistor (Q 3 ), in series with a second PNP transistor (Q 4 ) connected in diode mode and a current generator (Go), has its base connected to the base of the first NPN transistor (Q1), which is also the input terminal (IN) of the circuit. The base of the first PNP transistor (Q 2 ) is connected to the connection node (N) between the second PNP transistor (Q 4 ) and the current generator (Go).
    The circuit behaves as an excellent voltage follower with any type of load and requires a negligible use of area when it is formed as part of an integrated circuit.

    Abstract translation: 第一NPN晶体管（Q1）以射极跟随器配置连接有第一PNP晶体管（Q2）作为负载元件。 与二极管模式连接的第二PNP晶体管（Q4）和电流发生器（Go）串联的第二NPN晶体管（Q3）的基极连接到第一NPN晶体管（Q1）的基极，其也是 电路的输入端（IN）。 第一PNP晶体管（Q2）的基极连接到第二PNP晶体管（Q4）和电流发生器（Go）之间的连接节点（N）。 该电路作为具有任何类型负载的优异的电压跟随器，并且当其形成为集成电路的一部分时，需要可忽略的面积使用。

    An operational amplifier with high gain and sysmmetrical output-current capabilty
    15.
    发明公开
    An operational amplifier with high gain and sysmmetrical output-current capabilty 审中-公开
    EinOperationsverstärkermit hoherVerstärkungund symmetricrischem Ausgangsstrom

    公开(公告)号：EP1124326A1

    公开(公告)日：2001-08-16

    申请号：EP00830091.5

    申请日：2000-02-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Tomasini, Luciano ,  Clerici, Giancarlo

    IPC: H03F3/30

    CPC classification number: H03F3/3001

    Abstract: An operational amplifier comprises a first stage (2) and a second stage (3) with an input connected to an output (V oi ) of the first stage (2) and an output (Out) connectible to a load (RL), the second stage (3) comprising, between its input and its output, a first signal path (M 5 ) for driving the load (RL) in a first direction, and a second signal path (M 8 , M 3 , M 1 , M 2 , M 4 ) for driving the load (RL) in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

    Abstract translation: 运算放大器包括具有连接到第一级（2）的输出（Vo1）的输入和可连接到负载（RL）的输出（Out）的第一级（2）和第二级（3），第二级 在其输入和输出之间包括用于沿第一方向驱动负载（RL）的第一信号路径（M5）和用于驱动的​​第二信号路径（M8，M3，M1，M2，M4） 负载（RL）在相反的方向。 第一和第二信号路径对于小信号具有基本上相等的增益，对于小信号和大信号基本相等的输出阻抗以及基本相等的输出电流能力。

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