公开(公告)号：EP1113450A1

公开(公告)日：2001-07-04

申请号：EP99830825.8

申请日：1999-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zammattio, Matteo ,  Motta, Ilaria ,  Micheloni, Rino ,  Golla, Carla

IPC: G11C16/30 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: A voltage boost device includes a first boost stage (4) and a second boost stage (5) connected to an input terminal and to an output terminal (10), the output terminal (10) supplying an output voltage higher than a supply voltage. The input terminal receives an operating condition signal (SB) having a first logic level representative of a standby operating state and a second logic level representative of an active operation state. The first boost stage (4) is enabled in presence of the second logic level of the operating condition signal (SB), and is disabled in presence of the first logic level of the operating condition signal (SB); the second boost stage (5) is controlled in a first operating condition in presence of the first logic level of the operating condition signal (SB), and is controlled in a second operating condition in presence of the second logic level of the operating condition signal (SB).

Abstract translation: 升压装置包括连接到输入端和输出端（10）的第一升压级（4）和第二升压级（5），输出端（10）提供高于电源电压的输出电压。 输入端接收具有代表待机运行状态的第一逻辑电平的运行状态信号（SB）和表示主动运行状态的第二逻辑电平。 第一升压级（4）在存在操作条件信号（SB）的第二逻辑电平的情况下使能，并且在存在操作条件信号（SB）的第一逻辑电平的情况下被禁止; 在操作条件信号（SB）的第一逻辑电平存在的情况下，第二升压级（5）被控制在第一操作状态中，并且在操作状态信号的第二逻辑电平存在的情况下被控制在第二操作状态 （SB）。

公开(公告)号：EP0915477A1

公开(公告)日：1999-05-12

申请号：EP97830576.1

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maccarrone, Marco ,  Zammattio, Matteo

IPC: G11C8/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells.
The method consists of duplicating the ATD signal into at least one pair of signals (ATD1,ATD2) and propagating such signals through separate parallel timing chains (6,9) at the ends of which the ATD signal is reinstated, the chains (6,9) being alternately active.

Abstract translation: 本发明涉及一种方法和用于产生用于半导体集成电子存储器装置的定时存储单元读取相的脉冲同步信号（ATD）的电路。 的脉冲信号（ATD）在检测到所述存储单元的地址输入端的多个的至少一个的逻辑状态的变化的产生。 该ATD信号复制到至少一个对信号（ATD1，ATD2），并通过ATD信号纯粹是表示在其端部的分开的平行的定时链（6,9）传播搜索信号的方法besteht，所述链（6， 9）交替地处于活动状态。