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公开(公告)号:JPH06314816A
公开(公告)日:1994-11-08
申请号:JP10479993
申请日:1993-04-30
Applicant: SHARP KK
Inventor: MATSUO YOSHIHIKO , KUSUDA KAZUO , SADA NAOKI , YOSHIKAWA TOSHIBUMI , MATSUMURA TSUNEO
IPC: C08G77/00 , C08G77/02 , H01L21/56 , H01L23/29 , H01L23/31 , H01L31/0203 , H01L31/12 , H01L33/30 , H01L33/54 , H01L33/56 , H01L33/62 , H01L33/00
Abstract: PURPOSE:To provide compound semiconductor sealing resin which can prevent characteristic deterioration of a compound semiconductor chip. CONSTITUTION:A matrix of compound semiconductor sealing resin is siloxane compound which results in silicone resin by additive reaction. The resin contains a group comprised of a bonding of an organic group and an oxy-group. It is desirable that the group comprised of a combination between the organic group and the oxy-group is combined to a terminal end of molecule of siloxane compound such as an alkoxy group (-OR'). After a compound semiconductor chip is covered with compound semiconductor sealing resin, the compound semiconductor sealing resin is reacted under specified conditions to generate silicone resin and to chemically combine an element of a part of the compound semiconductor chip in contact with the silicone resin with siloxane group (-Si-O-) of the silicone resin.
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公开(公告)号:JPH0547989B2
公开(公告)日:1993-07-20
申请号:JP2323982
申请日:1982-02-15
Applicant: SHARP KK
Inventor: YOSHIKAWA TOSHIBUMI , NAKAKURA YUKINORI
IPC: H01L31/111 , H01L29/74 , H01L31/11
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公开(公告)号:JPH0519827B2
公开(公告)日:1993-03-17
申请号:JP24274084
申请日:1984-11-16
Applicant: SHARP KK
Inventor: YOSHIKAWA TOSHIBUMI , NAKAKURA YUKINORI , KAGISAWA ATSUSHI , NISHIMOTO NOBUHIRO
IPC: H01L29/78 , H01L21/82 , H01L27/118 , H01L29/06
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公开(公告)号:JPH0411772A
公开(公告)日:1992-01-16
申请号:JP11390990
申请日:1990-04-28
Applicant: SHARP KK
Inventor: MATSUNAMI MITSUO , MIYAJIMA TOSHIAKI , YOSHIOKA MINORU , YOSHIKAWA TOSHIBUMI , OKADA MASATAKE
IPC: H01L21/762 , H01L21/02 , H01L21/205 , H01L21/76 , H01L27/12 , H01L27/15 , H01L31/10
Abstract: PURPOSE:To form a high breakdown strength element and to improve reliability by increasing in thickness a single crystalline film formed insularly on a semiconductor in a selectively epitaxial manner, and forming a flattened buried layer between islands. CONSTITUTION:The surface of a silicon single crystalline substrate 1 is thermally oxidized to form an SiO2 film 2, and a plurality of dotlike openings 5 are formed in the film 2. An n-type silicon nonsingle crystalline film 3 is formed thereon, and further an SiO2 surface protective film 4 is formed. Then, the film 4 is removed by etching, a single crystalline film 6 is selectively etched to form a predetermined insular pattern. The insular semiconductor layer is increased in thickness by laminating the single crystalline thin film layer 6 electrically insulated by an insulating film from a plurality of substrates and an epitaxial layer 7 on the substrate 1. When the substrate 1 formed with flattened buried layer between the insular semiconductor layers is employed, its cost is reduced, and a high breakdown strength element is formed to enhance reliability.
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公开(公告)号:JPH02125666A
公开(公告)日:1990-05-14
申请号:JP27989988
申请日:1988-11-04
Applicant: SHARP KK
Inventor: YOSHIKAWA TOSHIBUMI
IPC: H01L29/74 , H01L27/08 , H01L29/747 , H03K17/725
Abstract: PURPOSE:To prevent failure of commutation by a method wherein an isolation region for preventing interference of minority carriers in an N-type substrate is provided between a pair of photo thyristors packaged in one chip. CONSTITUTION:A first photo thyristor made in a PNPN structure reaching from a first anode 22 of a first cathode 24 and a second photo thyristor made in a PNPN structure reaching from a second anode 25 to a second cathode 27 are provided in an N-type substrate 21. Moreover, an isolation region 30 is formed between these thyristors by selective diffusion of a heavy metal, such as Au, Pt and the like. Accordingly, in case the applying voltage is inverted, minority carriers in the substrate 21 on the side of the thyristor on one side are prevented from moving into the substrate 21 on the side of the thyristor on the other side by the region 30. Thereby, failure of commutation can be prevented.
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公开(公告)号:JPS6329422B2
公开(公告)日:1988-06-14
申请号:JP18845482
申请日:1982-10-26
Applicant: SHARP KK
Inventor: YOSHIKAWA TOSHIBUMI , SUZUKI HIROSHI
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公开(公告)号:JPS6255086B2
公开(公告)日:1987-11-18
申请号:JP9968578
申请日:1978-08-15
Applicant: SHARP KK
Inventor: TANI YOSHIHEI , YOSHIKAWA TOSHIBUMI , ASO AKIRA , KAWANABE HITOSHI
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公开(公告)号:JPS62131570A
公开(公告)日:1987-06-13
申请号:JP27231685
申请日:1985-12-03
Applicant: SHARP KK
Inventor: YAMAMOTO MOTOHIKO , KUBO MASARU , YOSHIKAWA TOSHIBUMI
IPC: H01L27/14 , H01L27/144
Abstract: PURPOSE:To shorten the accumulating time of minority carriers by the drawing effect of the minority carriers, which are injected from circuit elements and to make the response speed of a semiconductor light receiving device more quicker, by providing a P-N junction, which is formed by heteropolar embedded diffused layers beneath a signal processing circuit element. CONSTITUTION:Heteropolar first embedded diffused layers 9a and 9b are individually formed between a semiconductor substrate 1 and a lower epitaxial layer 7 beneath a photodiode 3 and a transistor 4. The embedded diffused layer 9a has a P-type. Both side surfaces of the upper part of the layer 9a reach isolating and diffusing layers 6. Meanwhile, the embedded diffused layer 9b has an N-type. An N-type second embedded diffused layer 10, which shows heteropolar property with respect to the embedded diffused layer 9a, is formed between the lower epitaxial layer 7 beneath the transistor 4 and an upper epitaxial layer 8. The lower part of the embedded diffused layer 10 reaches the upper part of the embedded diffused layer 9a. The boundary part between both embedded diffused layers 9a and 10 is a P-N junction.
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公开(公告)号:JPS6216367B2
公开(公告)日:1987-04-13
申请号:JP5841779
申请日:1979-05-11
Applicant: SHARP KK
Inventor: YOSHIKAWA TOSHIBUMI , TANI YOSHIHEI
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公开(公告)号:JPS60240174A
公开(公告)日:1985-11-29
申请号:JP9802884
申请日:1984-05-15
Applicant: SHARP KK
Inventor: YOSHIKAWA TOSHIBUMI , KUBO MASARU , KAGISAWA ATSUSHI , NISHIMOTO NOBUHIRO
IPC: H01L31/12 , H01L27/144 , H01L31/10
Abstract: PURPOSE:To prevent erroneous operation due to the effect of electrostatic coupling between a light emitting element and a light receiving element, by forming an N region in the most part of the surface layer part of the P type region in the N type region and the N type region of a photodiode. CONSTITUTION:The regions of N type layers 34 and 35 in a photodiode part (b) are expanded. The surface of a P type region 26 except a required part is covered by the N type layers 34 and 35. At this time, the N type diffused layers 34 and 35 are usually formed at the same time as the formation of emitter regions 28, 28,... in bipolar IC parts (a), (c),.... As a result, the N type layers 34 and 35 are connected to Vcc or a constant potential. Therefore, the photodiode part is electrostatically shielded by the N type layers 34 and 35. For example, with respect to the bipolar IC parts, an SiO2 film 31 and Al wiring are covered by a polyimide resin 32 and the Al wiring is insulated. A second Al electrode 33 is further formed thereon, and its potential is fixed to GND or to a constant potential. As a result, the IC part beneath the second Al electrode 33 is shielded from the photodiode.
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