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    VERTICAL INSULATED GATE TYPE FIELD EFFECT SEMICONDUCTOR DEVICE
    3.
    发明专利
    VERTICAL INSULATED GATE TYPE FIELD EFFECT SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS62101077A

    公开(公告)日：1987-05-11

    申请号：JP24216085

    申请日：1985-10-28

    Applicant: SHARP KK

    Inventor： YOSHIKAWA TOSHIBUMI ,  OKADA KEIICHI ,  KUBO MASARU ,  YOSHIOKA MINORU ,  ITO TAKUYA

    IPC: H01L29/08 ,  H01L29/78

    Abstract: PURPOSE:To obtain a high dielectric strength VD-MOS-FET whose ON resistance is reduced without increasing the chip size by providing an impurity region with a low specific resistivity in the surface part of an epitaxial layer. CONSTITUTION:In a powder VD-MOS-FET, the bottom surface of an N type semiconductor substrate 1 is used as a drain 2 and an N-type epitaxial layer 3 is formed on its top surface and P-type base regions 4 are formed in the parts of its surface part and N type regions 5 with a low specific resistivity are formed in the parts of the surface parts of the P-type base regions 4 as sources 6. A gate 9 is provided above a channel region 7, which is the other part of the surface part of the P-type region 4, with an SiO2 film 8 in between. An N type impurity region 12 with a low specific resistivity is formed in the surface part of the epitaxial layer 3 between the base regions 4. As the impurity region 12 is provided, the ON resistance at that part is significantly reduced so that the whole ON resistance can be reduce without increasing the chip size.

    SEMICONDUCTOR DEVICE
    4.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH0411772A

    公开(公告)日：1992-01-16

    申请号：JP11390990

    申请日：1990-04-28

    Applicant: SHARP KK

    Inventor： MATSUNAMI MITSUO ,  MIYAJIMA TOSHIAKI ,  YOSHIOKA MINORU ,  YOSHIKAWA TOSHIBUMI ,  OKADA MASATAKE

    IPC: H01L21/762 ,  H01L21/02 ,  H01L21/205 ,  H01L21/76 ,  H01L27/12 ,  H01L27/15 ,  H01L31/10

    Abstract: PURPOSE:To form a high breakdown strength element and to improve reliability by increasing in thickness a single crystalline film formed insularly on a semiconductor in a selectively epitaxial manner, and forming a flattened buried layer between islands. CONSTITUTION:The surface of a silicon single crystalline substrate 1 is thermally oxidized to form an SiO2 film 2, and a plurality of dotlike openings 5 are formed in the film 2. An n-type silicon nonsingle crystalline film 3 is formed thereon, and further an SiO2 surface protective film 4 is formed. Then, the film 4 is removed by etching, a single crystalline film 6 is selectively etched to form a predetermined insular pattern. The insular semiconductor layer is increased in thickness by laminating the single crystalline thin film layer 6 electrically insulated by an insulating film from a plurality of substrates and an epitaxial layer 7 on the substrate 1. When the substrate 1 formed with flattened buried layer between the insular semiconductor layers is employed, its cost is reduced, and a high breakdown strength element is formed to enhance reliability.

    LIGHT-ACTIVATED SEMICONDUCTOR DEVICE
    5.
    发明专利
    LIGHT-ACTIVATED SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH0244779A

    公开(公告)日：1990-02-14

    申请号：JP19634388

    申请日：1988-08-05

    Applicant: SHARP KK

    Inventor： MATSUNAMI MITSUO ,  MIYAJIMA TOSHIAKI ,  YOSHIOKA MINORU ,  KIOI KAZUMASA ,  DOI TSUKASA

    IPC: H01L31/10 ,  H01L21/336 ,  H01L29/78 ,  H01L31/04 ,  H01L31/12

    Abstract: PURPOSE:To decrease the cost of manufacturing by forming a high voltage output type solar battery with an Si layer comprising polycrystalline Si or single crystal Si. CONSTITUTION:A poly Si film 4 is formed on an SiO2 film 6 which is formed by a thermal oxidation method. The poly Si film 4 is formed by an SiH4 thermal decomposition method. The gate part of a vertical MOS FET comprising an SiO2 gate insulating film and a poly Si film 8 is fabricated by removing unnecessary parts of the SiO2 film and the poly Si film. An N -Si diffused layers 9 and 9' are formed in the source contact region of the vertical MOS FET and a part which is to become the light receiving surface of a solar battery. The SiO2 film 6, a P-Si diffused layer 5'' and the Si layer 4 in a specified pattern are sequentially removed. Each island shaped region in which the solar call element is assembled is isolated. Thereafter, an insulating film 10 comprising SiO2 and the like is formed by a low temperature CVD method and the like. In this way, the number of chips which are mounted in the package of a photo MOS relay is decreased, and the reliability is improved.

    OPTICAL COUPLING TYPE SEMICONDUCTOR RELAY DEVICE
    6.
    发明专利
    OPTICAL COUPLING TYPE SEMICONDUCTOR RELAY DEVICE 失效

    公开(公告)号：JPH0216778A

    公开(公告)日：1990-01-19

    申请号：JP16643888

    申请日：1988-07-04

    Applicant: SHARP KK

    Inventor： MIYAJIMA TOSHIAKI ,  KIOI KAZUMASA ,  MATSUNAMI MITSUO ,  DOI TSUKASA ,  YOSHIOKA MINORU ,  KOBA MASAYOSHI

    IPC: H01L31/10 ,  H01L31/12 ,  H03K17/78

    Abstract: PURPOSE:To miniaturize the device by laminating a photoelectric converter element on a longitudinal MOSFET through an insulating film, and forming the longitudinal MOSFET on a single semiconductor substrate so as to also use the substrate as a drain. CONSTITUTION:A light emitting section 4 and an optical detector section are disposed in opposition in the vicinities of the tip ends of lead frames 2, 3. Resin 6 is disposed between the light emitting section 4 and the optical detector section 5, the resin being capable of transmission of light emitted from the light emitting section 4. A longitudinal MOSFETs 8, 9 where photodiode arrays are laminated through insulating films are formed on the same semiconductor substrate 10. These FETs are connected to each other by using in common the substrate 10 as a drain.

    SEMICONDUCTOR DEVICE
    7.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH06181315A

    公开(公告)日：1994-06-28

    申请号：JP33310092

    申请日：1992-12-14

    Applicant: SHARP KK

    Inventor： YOSHIOKA MINORU

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/784

    Abstract: PURPOSE:To decrease the resistance on the part where a drain electrode will be provided and also to decrease an ON-resistance in total by a method wherein a plurality of recesses and protrusions are provided on the surface where a drain electrode is to be formed, and the impurities of the same conductivity type as the above-mentioned electrode-forming part are ion-implanted on the whole roughened surface. CONSTITUTION:A drain substrate 1, having the low resistance back side, is polished and a plurality of recesses and protrusions are formed on the back side of the drain substrate 1 using an anisotropic etchant. Then, the impurities such as phosphorus and the like having the same conductivity type as that of the drain substrate 1 are ion-implanted on the surface of the roughened drain substrate 1. After an electrode metal, which becomes a drain electrode 9, has been formed by vacuum deposition and the like, a heat treatment is conducted at 440 deg.C or thereabout, and the manufacturing process is completed. As a result, the contact resistance of the drain electrode 9 can be decreased, and the ON-resistance of the semiconductor element can be reduced as a whole.

    POWER MOS-FET
    8.
    发明专利
    POWER MOS-FET 失效

    公开(公告)号：JPS6263472A

    公开(公告)日：1987-03-20

    申请号：JP20390085

    申请日：1985-09-13

    Applicant: SHARP KK

    Inventor： KUBO MASARU ,  OKADA KEIICHI ,  YOSHIOKA MINORU ,  ITO TAKUYA ,  YOSHIKAWA TOSHIBUMI

    IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

    Abstract: PURPOSE:To reduce ON resistance, by forming a groove in the back surface of a semiconductor substrate layer beneath a gate so that the groove penetrates through the substrate layer and cuts into an epitaxial layer, and forming a high concentration layer having the same conductivity type as the substrate layer in the substrate layer facing a drain electrode. CONSTITUTION:Anisotropic etching is performed in the back surface of a substrate layer 1 beneath each gate, and a groove 11 is formed. A high concentration N layer 12 is formed from the back surface side of the substrate layer 1, in which the groove 11 is formed. A drain electrode 10 is formed on the surface of the N layer 12. The groove 11 has the depth penetrating at least the substrate layer 1 and reaching an epitaxial layer 2. It is desirable that the depth of the groove is made as deep as possible in decreasing the ON resistance within a range the withstanding voltage can be maintained.

    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
    9.
    发明专利
    SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效

    公开(公告)号：JPH04284673A

    公开(公告)日：1992-10-09

    申请号：JP4928291

    申请日：1991-03-14

    Applicant: SHARP KK

    Inventor： MATSUNAMI MITSUO ,  YOSHIOKA MINORU ,  TSUJI HIDEYUKI ,  MIYAJIMA TOSHIAKI

    IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

    Abstract: PURPOSE:To provide low-specific resistance protrusions, which are formed in connection with a low-specific resistance semiconductor substrate, in the parts of the current paths of semiconductor devices in a high-specific resistance semiconductor layer, in which the vertical semiconductor devices, such as vertical power MOSFETs, are formed, for reducing the ON resistance of the semiconductor devices. CONSTITUTION:Low-specific resistance protrusions 12, which penetrate an n epitaxial layer 10 of a high specific resistance from the upper part of an n (100) single crystal silicon substrate of a low specific resistance and are made to project in current paths of devices in a layer 13, which is an N layer identical with the layer 10 and has said devices formed of p wells 3, n diffused layers 6, a gate film and the like, are provided. As currents in said devices are made to flow through the protrusions 12, the ON resistance of the semiconductor devices can be effectively reduced.

    VERTICAL TYPE POWER MOSFET
    10.
    发明专利
    VERTICAL TYPE POWER MOSFET 失效

    公开(公告)号：JPH04273167A

    公开(公告)日：1992-09-29

    申请号：JP3327791

    申请日：1991-02-28

    Applicant: SHARP KK

    Inventor： YOSHIOKA MINORU ,  MIYAJIMA TOSHIAKI ,  MATSUNAMI MITSUO ,  TSUJI HIDEYUKI

    IPC: H01L29/06 ,  H01L29/78

    Abstract: PURPOSE:To uniform characteristic of a product by forming a channel part to be formed by impurity diffusion on the self-alignment basis in the circumference of an aperture of a mesh gate in the uniform impurity concentration for total circumference thereof, using the mesh gate of polysilicon in a vertical power MOSFET as a mask. CONSTITUTION:In formation of a self-aligned channel part 10 through sequential ion implantation of two kinds of impurities using a mesh type gate electrode 5 of polysilicon formed at the surface of semiconductor substrate in manufacture of a vertical type power MOSFET, an angled part of unit cell of the aperture of a gate electrode 5 is formed as a curved part having a constant coefficient of curvature. Thereby, diffusing condition to the circumference by heat treatment of impurity implanted to the unit cell is unified and impurity concentration at the channel part 10 in the total circumference of unit cell is unified.

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