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公开(公告)号：US12212349B2
公开(公告)日：2025-01-28
申请号：US18474395
申请日：2023-09-26
Applicant: Silicon Laboratories Inc.
Inventor： Euisoo Yoo , Arup Mukherji , Rangakrishnan Srinivasan , Vitor Pereira , Zhongda Wang , Sriharsha Vasadi
Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
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12.发明公开公开(公告)号：US20240244572A1
公开(公告)日：2024-07-18
申请号：US18618458
申请日：2024-03-27
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , John Khoury
Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by disposing the divider outside the phase locked loop and using the output of the divider to create the clocks for both the transmit circuit and receive circuit. In another embodiment, one or more dividers are disposed outside the phase locked loop, each having a reset, such that they can be initialized to a predetermined state. Further, by utilizing a divider with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.
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公开(公告)号：US11804862B2
公开(公告)日：2023-10-31
申请号：US17490255
申请日：2021-09-30
Applicant: Silicon Laboratories Inc.
Inventor： Euisoo Yoo , Arup Mukherji , Rangakrishnan Srinivasan , Vitor Pereira , Zhongda Wang , Sriharsha Vasadi
CPC classification number: H04B1/0064 , H03F3/195 , H03H7/38 , H03F2200/294 , H03F2200/451
Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.
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公开(公告)号：US11444627B1
公开(公告)日：2022-09-13
申请号：US17549314
申请日：2021-12-13
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Michael Wu , Francesco Barale , John Khoury , Aslamali A. Rafi
Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.
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公开(公告)号：US20190229684A1
公开(公告)日：2019-07-25
申请号：US15875274
申请日：2018-01-19
Applicant: Silicon Laboratories Inc.
Inventor： Sherry X. Wu , Sriharsha Vasadi , Mustafa H. Koroglu , Rangakrishnan Srinivasan
Abstract: In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.
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Patent Agency Ranking
公开(公告)号：US20170359076A1
公开(公告)日：2017-12-14
申请号：US15370742
申请日：2016-12-06
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Rangakrishnan Srinivasan , Francesco Barale
CPC classification number: H03L7/183 , H03L7/0891 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L2207/06
Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.
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17.发明公开公开(公告)号：US20240267005A1
公开(公告)日：2024-08-08
申请号：US18639872
申请日：2024-04-18
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Mustafa H. Koroglu , Zhongda Wang , Francesco Barale , Abdulkerim L. Coban , John M. Khoury , Sriharsha Vasadi , Michael S. Johnson , Vitor Pereira
CPC classification number: H03F1/26 , H03B5/04 , H03F1/30 , H03F3/245 , H03K5/00 , H03F2200/375 , H03K2005/00019
Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.
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公开(公告)号：US12028024B2
公开(公告)日：2024-07-02
申请号：US16705868
申请日：2019-12-06
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Mustafa H. Koroglu , Zhongda Wang , Francesco Barale , Abdulkerim L Coban , John M. Khoury , Sriharsha Vasadi , Michael S. Johnson , Vitor Pereira
CPC classification number: H03F1/26 , H03B5/04 , H03F1/30 , H03F3/245 , H03K5/00 , H03F2200/375 , H03K2005/00019
Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.
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公开(公告)号：US20240110972A1
公开(公告)日：2024-04-04
申请号：US18174003
申请日：2023-02-24
Applicant: Silicon Laboratories Inc.
Inventor： Anant Verma , Rangakrishnan Srinivasan , Zhongda Wang
CPC classification number: G01R31/2824 , H04B17/14 , H04L27/12
Abstract: Modulation testing separately enables slices of an analog varactor array of an LC oscillator. For each enabled slice, a reference voltage supplying a resistor ladder is set to a plurality of different reference voltage values. Resistor ladder voltages generated for the different reference voltage values are supplied to the enabled slice and a control voltage coupled to the enabled slice is swept for each of the reference voltage values. Respective frequencies of an oscillator signal coupled to an output of the LC oscillator are measured for each enabled slice for each combination of the reference voltage values and the control voltage values. The linearity of LC oscillator gain is determined for each of the reference voltage values for each slice based on the respective frequencies and the control voltage values. Passing/failing the modulation testing is based on the linearity of the LC oscillator gain.
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公开(公告)号：US20240106398A1
公开(公告)日：2024-03-28
申请号：US17955171
申请日：2022-09-28
Applicant: Silicon Laboratories Inc.
Inventor： Rangakrishnan Srinivasan , Sriharsha Vasadi , Mustafa Koroglu , Zhongda Wang , Euisoo Yoo , Eddy Bell
CPC classification number: H03F3/245 , H04B1/0475 , H03F2200/451
Abstract: In one aspect, an apparatus comprises: a driver circuit to receive first and second ramp signals and output first and second drive signals under control of a first bias signal and a second bias signal, the first bias signal having a first edge and a second edge, the second edge having a different edge rate than the first edge, the second bias signal having a third edge and a fourth edge, the third edge having a different edge rate than the fourth edge; and an output circuit coupled to the driver circuit, the output circuit comprising at least one first active device to be driven by the first drive signal and at least one second active device to be driven by the second drive signal, where the output circuit is to amplify and output a radio frequency (RF) signal.
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