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    13.
    发明专利
    未知

    公开(公告)号：DE69025795T2

    公开(公告)日：1996-08-22

    申请号：DE69025795

    申请日：1990-05-02

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W

    IPC: H01L21/82 ,  G11C29/00 ,  H03K19/173 ,  G06F11/20 ,  G06F11/18

    Abstract: A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.

    MICROINSTRUCTION SEQUENCER
    17.
    发明专利
    MICROINSTRUCTION SEQUENCER 未知

    公开(公告)号：AU6697090A

    公开(公告)日：1991-05-30

    申请号：AU6697090

    申请日：1990-11-26

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W ,  RAHMAN MIZANUR M ,  HARRIS RICHARD

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28

    Abstract: First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. In one embodiment of the invention, the contents of the vertical control store are logically offset from their original address by 1 whereas the contents of the horizontal control store and the jump control store are aligned with their original address. In another embodiment, the contents of the horizontal control store and the jump control store are offset from their original addresses by one, whereas the contents of the vertical control store are aligned with their original addresses. This allows simultaneous accessing of different microinstructions using a single address counter. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The contents of the two banks are the same to provide soft error coverage and recovery. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines. When processing trap routines, the return address stack stores two microinstruction addresses to allow processing of a previously encountered jump or call operation that may have been aborted when the trap routine was entered.

    DEFERRED COMPARISON MULTIPLIER CHECKER
    18.
    发明专利
    DEFERRED COMPARISON MULTIPLIER CHECKER 未知

    公开(公告)号：AU5889590A

    公开(公告)日：1991-01-17

    申请号：AU5889590

    申请日：1990-07-11

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W ,  JARDINE ROBERT L

    IPC: G06F7/499 ,  G06F7/00 ,  G06F7/53 ,  G06F11/14

    Abstract: In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for used, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.

    LINEAR ARRAY WAFER SCALE INTEGRATION ARCHITECTURE
    19.
    发明专利
    LINEAR ARRAY WAFER SCALE INTEGRATION ARCHITECTURE 未知

    公开(公告)号：CA2015853A1

    公开(公告)日：1990-11-02

    申请号：CA2015853

    申请日：1990-05-01

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W

    IPC: H01L21/82 ,  G11C29/00 ,  H03K19/173 ,  H03K19/08 ,  H03K19/0175

    Abstract: A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.

    HIGH-PERFORMANCE COMPUTER SYSTEM WITH FAULT-TOLERANT CAPABILITY
    20.
    发明专利
    HIGH-PERFORMANCE COMPUTER SYSTEM WITH FAULT-TOLERANT CAPABILITY 未知

    公开(公告)号：CA2003337A1

    公开(公告)日：1990-06-09

    申请号：CA2003337

    申请日：1989-11-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W JR ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN D ,  HORST ROBERT W

    IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors arc coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

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