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    MEMORY MANAGEMENT IN HIGH-PERFORMANCE FAULT-TOLERANT COMPUTER SYSTEMS
    2.
    发明专利
    MEMORY MANAGEMENT IN HIGH-PERFORMANCE FAULT-TOLERANT COMPUTER SYSTEMS 未知

    公开(公告)号：AU628497B2

    公开(公告)日：1992-09-17

    申请号：AU5202790

    申请日：1990-03-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W ,  ALLISON JOHN DAVID ,  MEHTA NIKHIL A ,  DEBACKER KENNETH C ,  JEWETT DOUGLAS E ,  PEET CHARLES E JR ,  CUTTS RICHARD W JR

    IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00 ,  G06F12/08

    Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

    3.
    发明专利
    未知

    公开(公告)号：AT158879T

    公开(公告)日：1997-10-15

    申请号：AT89122708

    申请日：1989-12-08

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W JR ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

    IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

    Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

    HIGH-PERFORMANCE COMPUTER SYSTEM WITH FAULT-TOLERANT CAPABILITY
    4.
    发明专利
    HIGH-PERFORMANCE COMPUTER SYSTEM WITH FAULT-TOLERANT CAPABILITY 未知

    公开(公告)号：CA2003337A1

    公开(公告)日：1990-06-09

    申请号：CA2003337

    申请日：1989-11-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W JR ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN D ,  HORST ROBERT W

    IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors arc coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

    FAULT-TOLERANT COMPUTER SYSTEM WITH ONLINE REINTEGRATION AND SHUTDOWN/RESTART
    5.
    发明专利
    FAULT-TOLERANT COMPUTER SYSTEM WITH ONLINE REINTEGRATION AND SHUTDOWN/RESTART 未知

    公开(公告)号：CA2032067A1

    公开(公告)日：1991-06-23

    申请号：CA2032067

    申请日：1990-12-12

    Applicant: TANDEM COMPUTERS INC

    Inventor： JEWETT DOUGLAS E ,  BEREITER TOM ,  VETTER BRIAN ,  BANTON RANDALL G ,  CUTTS RICHARD W JR ,  WESTBROOK DONALD C ,  FEY KYRAN W JR ,  POZDRO JOHN ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  WEBSTER PHIL ,  ALDRIDGE DAVE ,  NORWOOD PETER C

    IPC: G06F1/12 ,  G06F1/30 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/22 ,  G06F11/273

    Abstract: FAULT-TOLERANT COMPUTER SYSTEM WITH ONLINE REINTEGRATION AND SHUTDOWN/RESTART A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit of offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. The system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.

    8.
    发明专利
    未知

    公开(公告)号：DE68928360T2

    公开(公告)日：1998-05-07

    申请号：DE68928360

    申请日：1989-12-08

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

    Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

    SYNCHRONIZATION OF FAULT-TOLERANT COMPUTER SYSTEM HAVING MULTIPLE PROCESSORS
    9.
    发明专利
    SYNCHRONIZATION OF FAULT-TOLERANT COMPUTER SYSTEM HAVING MULTIPLE PROCESSORS 未知

    公开(公告)号：AU625293B2

    公开(公告)日：1992-07-09

    申请号：AU5202590

    申请日：1990-03-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： SOUTHWORTH RICHARD A ,  CUTTS RICHARD W ,  HORST ROBERT W ,  ALLISON JOHN DAVID ,  MEHTA NIKHIL A ,  DEBACKER KENNETH C ,  JEWETT DOUGLAS E

    IPC: G06F1/12 ,  G06F9/46 ,  G06F11/16

    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

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