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    DEFERRED COMPARISON MULTIPLIER CHECKER
    2.
    发明专利
    DEFERRED COMPARISON MULTIPLIER CHECKER 未知

    公开(公告)号：AU5889590A

    公开(公告)日：1991-01-17

    申请号：AU5889590

    申请日：1990-07-11

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W ,  JARDINE ROBERT L

    IPC: G06F7/499 ,  G06F7/00 ,  G06F7/53 ,  G06F11/14

    Abstract: In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for used, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.

    DISTRIBUTED AGREEMENT ON PROCESSOR MEMBERSHIP IN A MULTI-PROCESSOR SYSTEM
    3.
    发明专利
    DISTRIBUTED AGREEMENT ON PROCESSOR MEMBERSHIP IN A MULTI-PROCESSOR SYSTEM 未知

    公开(公告)号：CA2275241A1

    公开(公告)日：1998-07-30

    申请号：CA2275241

    申请日：1998-01-23

    Applicant: TANDEM COMPUTERS INC

    Inventor： BASAVAIAH MURALI ,  JARDINE ROBERT L ,  KRISHNAKUMAR KAROOR S ,  MURTHY SRINIVASA D

    IPC: G06F11/20 ,  G06F11/00 ,  G06F11/14 ,  G06F13/00

    Abstract: A system to determine the group of processors that will survive communications faults and/or timed-event failures in a multi-processor system (100). The processors (112), each having a memory (118) and connected to an interprocessor communication network (114), detect that the set of processors with which they can communicate has changed. They then choose to halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems on the initiation of a regroup operation (622b). A processor is suspected of having failed when other processors detect the absence of a periodic message from the processor (682). When this happens, all of the processors are subjected to a series of stages in which they repeatedly broadcast their status and connectivity to each other (830). The suspected processor does not advance through the stages to regroup if it has ceased operations or if its timer mechanism has failed.

    4.
    发明专利
    未知

    公开(公告)号：DE69022144T2

    公开(公告)日：1996-03-14

    申请号：DE69022144

    申请日：1990-07-02

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W ,  JARDINE ROBERT L

    IPC: G06F7/499 ,  G06F7/00 ,  G06F7/53 ,  G06F11/14 ,  G06F11/16

    Abstract: In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for used, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.

    5.
    发明专利
    未知

    公开(公告)号：DE69028138D1

    公开(公告)日：1996-09-26

    申请号：DE69028138

    申请日：1990-05-21

    Applicant: TANDEM COMPUTERS INC

    Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

    IPC: G06F9/38

    Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

    PAIRED INSTRUCTION PROCESSOR PRECISE EXCEPTION HANDLING MECHANISM
    6.
    发明专利
    PAIRED INSTRUCTION PROCESSOR PRECISE EXCEPTION HANDLING MECHANISM 未知

    公开(公告)号：CA2016252A1

    公开(公告)日：1990-11-24

    申请号：CA2016252

    申请日：1990-05-08

    Applicant: TANDEM COMPUTERS INC

    Inventor： JARDINE ROBERT L ,  LYNCH SHANNON J ,  MANELA PHILIP R ,  HORST ROBERT W

    IPC: G06F9/38 ,  G06F9/22 ,  G06F9/312

    Abstract: PAIRED INSTRUCTION PROCESSOR E EXCEPTION HANDLING MECHANISM A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized. T18/10577-211

    METHOD FOR KEEPING ACCURATE TIME IN A COMPUTER SYSTEM
    8.
    发明专利
    METHOD FOR KEEPING ACCURATE TIME IN A COMPUTER SYSTEM 未知

    公开(公告)号：CA2263402A1

    公开(公告)日：1998-02-12

    申请号：CA2263402

    申请日：1997-08-07

    Applicant: TANDEM COMPUTERS INC

    Inventor： MOIIN HOSSEIN ,  JARDINE ROBERT L

    IPC: G04G3/00 ,  G04G5/00 ,  G06F1/14

    Abstract: A computing system develops time/date values by using a free-running counter to measure and accumulate increments of time. The increments of time are converted from the resolution of the free-running counter to that used for the time and date values by dividing by a conversion variable and then used to update the time/date value. The accuracy of the time/date value is monitored by periodically comparing the rate of the free-running counter to the rate of a more accurate, external clock. The ratio of these two rates is used to adjust the conversion variable. The conversion variable reflects any differences between (1) the rate of change of the increments of time used for developing the time/data value and (2) the external clock. Its use here, therefore, will operate to either slow down or speed up the rate of change of the time/date value so that it more closely tracks the external clock.

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