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    TRANSPOSE TABLE BIASED ARBITRATION SCHEME
    1.
    发明申请
    TRANSPOSE TABLE BIASED ARBITRATION SCHEME 审中-公开

    公开(公告)号：WO9959048A9

    公开(公告)日：2000-03-02

    申请号：PCT/US9910607

    申请日：1999-05-13

    Applicant: TANDEM COMPUTERS INC

    Inventor： SONNIER DAVID P ,  WATSON WILLIAM J ,  MIZELL ROBERT B ,  HORST ROBERT W

    IPC: G06F13/364 ,  H04L12/56 ,  G06F

    CPC classification number: G06F13/364 ,  H04L47/24

    Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias values are granted more frequent access to the shared resource. A look-ahead feature skips rows having all zeros and an unbiased cycle that assures all requesting ports are serviced regardless of their bias values.

    Abstract translation: 偏向仲裁技术利用转置表仲裁对共享资源的访问。 转置表的每一列是编码分配给其中一个请求者的偏移值的二进制偏差向量。 提取表的行以确保具有高偏差值的请求者被更频繁地访问共享资源。 先行功能跳过具有全零和不偏倚周期的行，确保所有请求端口都被服务，而不管其偏差值如何。

    3.
    发明专利
    未知

    公开(公告)号：DE68928360D1

    公开(公告)日：1997-11-06

    申请号：DE68928360

    申请日：1989-12-08

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

    IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

    Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

    MEMORY MANAGEMENT IN HIGH-PERFORMANCE FAULT-TOLERANT COMPUTER SYSTEM
    5.
    发明专利
    MEMORY MANAGEMENT IN HIGH-PERFORMANCE FAULT-TOLERANT COMPUTER SYSTEM 未知

    公开(公告)号：CA2003342A1

    公开(公告)日：1990-06-09

    申请号：CA2003342

    申请日：1989-11-20

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W JR ,  PEET CHARLES E JR ,  JEWETT DOUGLAS E ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN D ,  HORST ROBERT W

    IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00 ,  G06F13/00 ,  G06F13/36

    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number Or I/O processors are coupled to both I/O busses. Each CPU has its own fast cache and also a local memory not accessible by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernel is kept in local memory. A private-write area is included in the shared memory space in the memory modules to allow functions such as software voting of state information unique to CPUs. All CPUs write state information to their private-write area, then all CPUs read all the private-write areas for functions such as detecting differences in interrupt cause or the like.

    CACHE MEMORY SUPPORTING FAST UNALIGNED ACCESS
    7.
    发明专利
    CACHE MEMORY SUPPORTING FAST UNALIGNED ACCESS 未知

    公开(公告)号：CA2000031A1

    公开(公告)日：1990-04-20

    申请号：CA2000031

    申请日：1989-10-02

    Applicant: TANDEM COMPUTERS INC

    Inventor： HORST ROBERT W

    IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0886 ,  G06F12/0895 ,  G06F12/109 ,  G06F13/00

    Abstract: CACHE MEMORY SUPPORTING FAST UNALIGNED ACCESS A cache system that fetches aligned and unaligned references in one cache cycle that includes a separate memory unit for each word included in the multiword data unit fetched during one reference. Memory processing hardware responsive to the word address of a first word to be fetched fetches a sequence of words following the first word from the memory units. The address field identifying the position of the first word in the multiword data unit is utilized to order the words fetched from the memory units to correspond to the order of the words in the sequence to be fetched. T14/10577-175

    10.
    发明专利
    未知

    公开(公告)号：AT158879T

    公开(公告)日：1997-10-15

    申请号：AT89122708

    申请日：1989-12-08

    Applicant: TANDEM COMPUTERS INC

    Inventor： CUTTS RICHARD W JR ,  BANTON RANDALL G ,  JEWETT DOUGLAS E ,  NORWOOD PETER C ,  DEBACKER KENNETH C ,  MEHTA NIKHIL A ,  ALLISON JOHN DAVID ,  HORST ROBERT W

    IPC: G06F11/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F12/02 ,  G06F15/16 ,  G06F15/17 ,  G11C29/00

    Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

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