公开(公告)号：FR2547082A1

公开(公告)日：1984-12-07

申请号：FR8404937

申请日：1984-03-29

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F3/04

公开(公告)号：CA1147824A

公开(公告)日：1983-06-07

申请号：CA391317

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F15/16

Abstract: A datapath system and protocol is disclosed in which data is transferred between a computer memory and one or more peripheral devices through device controllers, each of which includes a buffer, through periodic connection of the device controller to the channel. The system and protocol are structured to permit multiple device controllers to cooperatively interact on a single channel, without direct communication between device controllers. Each device controller monitors the level of stress on its buffer and at appropriate times presents a reconnect request to the channel, together with indicia for permitting the channel to determine the priority of a particular request relative to other reconnect requests. The times at which a reconnect signal should be presented are determined by monitoring the level of information storage in the buffer and relating that level to a threshold level; both overfilling and overemptying are prevented. The threshold level can be varied in accordance with a criteria which makes allowance for the number and combination of device controllers attached to the channel; and is set such that the remaining space in the buffer is sufficient to allow the buffer to transfer data to or from the associated peripheral device, at the rate demanded by that peripheral device, long enough to allow the channel to connect to one lower priority device controller, and all higher priority device controllers. The threshold level and buffer size are also set such that, after a reconnect, the buffer is capable of transferring data to or from the associated peripheral device, at the rate demanded by the peripheral, long enough for the channel to reconnect to all lower priority device controllers, to ensure that all device controllers, no matter the priority, are allowed access to the channel. The invention has broad application, but is particularly well-suited to fault tolerant computing systems.

公开(公告)号：CA1136728A

公开(公告)日：1982-11-30

申请号：CA391319

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: H04L5/14

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：DE3752205T2

公开(公告)日：1999-04-22

申请号：DE3752205

申请日：1987-03-13

Applicant: TANDEM COMPUTERS INC

Inventor： LILJA DAVID J DEPT OF ELECTRIC ,  ZACHER RICHARD A ,  WIERENGA STEVEN W

IPC: G06F11/20 ,  G06F13/22 ,  G06F13/42 ,  G06F15/16

Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

公开(公告)号：DE3750680D1

公开(公告)日：1994-12-01

申请号：DE3750680

申请日：1987-03-13

Applicant: TANDEM COMPUTERS INC

Inventor： LILJA DAVID J ,  ZACHER RICHARD A ,  WIERENGA STEVEN W

IPC: G06F11/20 ,  G06F13/22 ,  G06F13/42 ,  G06F15/16

Abstract: A bus protocol system for interprocessor communications. The protocol system polls the processors in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processors are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

公开(公告)号：CA1185670A

公开(公告)日：1985-04-16

申请号：CA455620

申请日：1984-05-31

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F3/00

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multlprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：CA1147417A

公开(公告)日：1983-05-31

申请号：CA391320

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F15/16

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：CA1135809A

公开(公告)日：1982-11-16

申请号：CA391314

申请日：1981-12-01

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: H04L5/14

Abstract: A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures uninterrupted operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

公开(公告)号：CA1121481A

公开(公告)日：1982-04-06

申请号：CA280505

申请日：1977-06-14

Applicant: TANDEM COMPUTERS INC

Inventor： KATZMAN JAMES A ,  BARTLETT JOEL F ,  BIXLER RICHARD M ,  DAVIDOW WILLIAM H ,  DESPOTAKIS JOHN A ,  GRAZIANO PETER J ,  GREEN MICHAEL D ,  GREIG DAVID A ,  HAYASHI STEVEN J ,  MACKIE DAVID R ,  MCEVOY DENNIS L ,  TREYBIG JAMES G ,  WIERENGA STEVEN W

IPC: G06F11/18 ,  G06F1/26 ,  G06F5/06 ,  G06F7/78 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G06F13/00 ,  G06F13/12 ,  G06F13/20 ,  G06F13/28 ,  G06F13/366 ,  G06F13/38 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

Abstract: MULTIPROCESSOR SYSTEM A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor module Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas -- user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system. The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.